PWM/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	2.300s	1.135m	7.262ms	10	10	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	0.830s	1.303m	15.770us	5	5	100.00
V1	csr_rw	pwm_csr_rw	0.740s	1.303m	18.015us	3	3	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	3.760s	1.420m	510.198us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	1.270s	1.369m	68.271us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	0.970s	1.453m	32.082us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	0.740s	1.303m	18.015us	3	3	100.00
		pwm_csr_aliasing	1.270s	1.369m	68.271us	5	5	100.00
V1		TOTAL				32	32	100.00
V2	dutycycle	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	pulse	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	blink	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	heartbeat	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	resolution	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	multi_channel	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	polarity	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	phase	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
		pwm_phase	19.190s	1.269m	29.477ms	9	9	100.00
V2	lowpower	pwm_rand_output	25.170s	1.419m	10.718ms	11	11	100.00
V2	perf	pwm_perf	22.270s	1.302m	21.305ms	4	4	100.00
V2	regwen	pwm_regwen	1.038m	1.636m	42.015ms	1	1	100.00
V2	stress_all	pwm_stress_all	1.505m	2.724m	171.987ms	21	21	100.00
V2	alert_test	pwm_alert_test	0.530s	1.169m	22.980us	3	3	100.00
V2	intr_test	pwm_intr_test				0	0	--
V2	tl_d_oob_addr_access	pwm_tl_errors	1.860s	1.369m	168.751us	3	3	100.00
V2	tl_d_illegal_access	pwm_tl_errors	1.860s	1.369m	168.751us	3	3	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	0.830s	1.303m	15.770us	5	5	100.00
		pwm_csr_rw	0.740s	1.303m	18.015us	3	3	100.00
		pwm_csr_aliasing	1.270s	1.369m	68.271us	5	5	100.00
		pwm_same_csr_outstanding	0.930s	1.453m	117.289us	3	3	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	0.830s	1.303m	15.770us	5	5	100.00
		pwm_csr_rw	0.740s	1.303m	18.015us	3	3	100.00
		pwm_csr_aliasing	1.270s	1.369m	68.271us	5	5	100.00
		pwm_same_csr_outstanding	0.930s	1.453m	117.289us	3	3	100.00
V2		TOTAL				55	55	100.00
V2S	tl_intg_err	pwm_tl_intg_err	1.410s	1.153m	209.839us	3	3	100.00
		pwm_sec_cm	0.720s	1.135m	250.549us	3	3	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	1.410s	1.153m	209.839us	3	3	100.00
V2S		TOTAL				6	6	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	22.320s	1.335m	21.005ms	11	11	100.00
V3		TOTAL				11	11	100.00
		TOTAL				104	104	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	8	8	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.82	99.65	94.10	91.96	--	98.93	98.00	80.30

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52