PWRMGR/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.540s	15.271s	26.330us	1	1	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.510s	13.212s	59.269us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.530s	13.215s	55.382us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	1.640s	14.295s	859.022us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.680s	14.219s	149.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	0.820s	13.227s	199.200us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.530s	13.215s	55.382us	20	20	100.00
		pwrmgr_csr_aliasing	0.680s	14.219s	149.488us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	wakeup	pwrmgr_wakeup	0.620s	18.290s	238.580us	1	1	100.00
V2	control_clks	pwrmgr_wakeup	0.620s	18.290s	238.580us	1	1	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.530s	18.264s	56.491us	1	1	100.00
		pwrmgr_lowpower_invalid	0.560s	15.191s	39.542us	3	3	100.00
V2	reset	pwrmgr_reset	0.600s	18.289s	76.637us	4	4	100.00
		pwrmgr_reset_invalid	0.620s	15.189s	123.542us	3	3	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.600s	18.289s	76.637us	4	4	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.640s	18.263s	240.546us	1	1	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.570s	18.290s	278.176us	1	1	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.590s	15.187s	45.810us	2	4	50.00
V2	stress_all	pwrmgr_stress_all	1.620s	14.149s	751.177us	1	1	100.00
V2	intr_test	pwrmgr_intr_test	0.500s	15.227s	59.024us	5	5	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	1.250s	16.248s	228.220us	3	3	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	1.250s	16.248s	228.220us	3	3	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.510s	13.212s	59.269us	5	5	100.00
		pwrmgr_csr_rw	0.530s	13.215s	55.382us	20	20	100.00
		pwrmgr_csr_aliasing	0.680s	14.219s	149.488us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.610s	13.207s	38.410us	3	3	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.510s	13.212s	59.269us	5	5	100.00
		pwrmgr_csr_rw	0.530s	13.215s	55.382us	20	20	100.00
		pwrmgr_csr_aliasing	0.680s	14.219s	149.488us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.610s	13.207s	38.410us	3	3	100.00
V2		TOTAL				28	30	93.33
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.020s	14.253s	210.489us	7	7	100.00
		pwrmgr_sec_cm	1.010s	16.155s	671.254us	3	3	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.010s	16.155s	671.254us	3	3	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.010s	16.155s	671.254us	3	3	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.020s	14.253s	210.489us	7	7	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.540s	16.248s	804.801us	7	7	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_wakeup_reset	0.640s	18.263s	240.546us	1	1	100.00
		pwrmgr_repeat_wakeup_reset				0	0	--
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.610s	15.236s	47.726us	1	1	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.510s	15.200s	32.259us	4	4	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.010s	16.155s	671.254us	3	3	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.010s	16.155s	671.254us	3	3	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.010s	16.155s	671.254us	3	3	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.480s	15.203s	83.284us	1	1	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.530s	15.181s	62.199us	3	3	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	0.650s	15.201s	115.394us	3	3	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.530s	13.215s	55.382us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.530s	13.215s	55.382us	20	20	100.00
V2S		TOTAL				29	29	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.590s	15.179s	375.185us	0	1	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	8.470s	19.248s	10.945ms	2	3	66.67
V3		TOTAL				2	4	50.00
		TOTAL				115	119	96.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	8	8	88.89
V3	2	2	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.50	99.24	96.72	96.87	96.00	97.39	97.47	70.84

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL (pwrmgr_base_vseq.sv:584) [pwrmgr_disable_rom_integrity_check_vseq] timeout waiting for pwrmgr fast fsm target activity has 2 failures:

  • Test pwrmgr_disable_rom_integrity_check has 2 failures.

    • 2.pwrmgr_disable_rom_integrity_check.4005121698196736148483037834536349855970541756285315645470428007546283474874
      Line 117, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_dragonfly-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @  62392908 ps: (pwrmgr_base_vseq.sv:584) [uvm_test_top.env.virtual_sequencer.pwrmgr_disable_rom_integrity_check_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @  62392908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.pwrmgr_disable_rom_integrity_check.22650955335303918720397127212555144500257294240896296972325254361234352195039
      Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_dragonfly-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @  52601454 ps: (pwrmgr_base_vseq.sv:584) [uvm_test_top.env.virtual_sequencer.pwrmgr_disable_rom_integrity_check_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @  52601454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!clk_en) || status)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 0.pwrmgr_escalation_timeout.87283058705944451656256197580238501002095688945521951091108083460647970012821
      Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_dragonfly-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

            Offending '((!clk_en) || status)'
        UVM_ERROR @ 375184601 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
        UVM_INFO @ 375184601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]' has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.51638196119191856358537669488580166790485491239171189198508179183418712675467
      Line 2672, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_dragonfly-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

            Offending 'rstreqs[pwrmgr_reg_pkg::ResetEscIdx]'
        UVM_ERROR @ 3052316372 ps: (pwrmgr_rstreqs_sva_if.sv:89) [ASSERT FAILED] EscRstOn_A
        UVM_INFO @ 3052316372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---