PWRMGR/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.520s	25.060s	40.272us	1	1	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.550s	37.141s	33.963us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.530s	35.128s	18.387us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	1.890s	36.139s	313.260us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	0.690s	35.133s	51.657us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	0.930s	35.105s	111.804us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.530s	35.128s	18.387us	20	20	100.00
		pwrmgr_csr_aliasing	0.690s	35.133s	51.657us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	wakeup	pwrmgr_wakeup	0.510s	39.069s	97.282us	1	1	100.00
V2	control_clks	pwrmgr_wakeup	0.510s	39.069s	97.282us	1	1	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.630s	40.080s	46.362us	1	1	100.00
		pwrmgr_lowpower_invalid	0.580s	41.157s	43.251us	3	3	100.00
V2	reset	pwrmgr_reset	0.810s	30.063s	1.000ms	0	1	0.00
		pwrmgr_reset_invalid	0.720s	39.153s	98.190us	2	3	66.67
V2	main_power_glitch_reset	pwrmgr_reset	0.810s	30.063s	1.000ms	0	1	0.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.790s	42.070s	241.291us	1	1	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.760s	35.066s	516.965us	1	1	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.880s	35.073s	1.000ms	0	1	0.00
V2	stress_all	pwrmgr_stress_all	3.350s	32.075s	1.671ms	1	1	100.00
V2	intr_test	pwrmgr_intr_test	0.510s	36.136s	31.037us	5	5	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	1.230s	40.130s	388.145us	3	3	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	1.230s	40.130s	388.145us	3	3	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.550s	37.141s	33.963us	5	5	100.00
		pwrmgr_csr_rw	0.530s	35.128s	18.387us	20	20	100.00
		pwrmgr_csr_aliasing	0.690s	35.133s	51.657us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.580s	35.131s	30.869us	3	3	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.550s	37.141s	33.963us	5	5	100.00
		pwrmgr_csr_rw	0.530s	35.128s	18.387us	20	20	100.00
		pwrmgr_csr_aliasing	0.690s	35.133s	51.657us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.580s	35.131s	30.869us	3	3	100.00
V2		TOTAL				21	24	87.50
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.000s	40.136s	227.210us	4	4	100.00
		pwrmgr_sec_cm	1.060s	40.155s	700.860us	3	3	100.00
V2S	prim_count_check	pwrmgr_sec_cm	1.060s	40.155s	700.860us	3	3	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	1.060s	40.155s	700.860us	3	3	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.000s	40.136s	227.210us	4	4	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.680s	40.143s	866.491us	4	4	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_wakeup_reset	0.790s	42.070s	241.291us	1	1	100.00
		pwrmgr_repeat_wakeup_reset				0	0	--
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.660s	37.075s	48.662us	1	1	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.530s	39.153s	30.556us	3	3	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	1.060s	40.155s	700.860us	3	3	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	1.060s	40.155s	700.860us	3	3	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	1.060s	40.155s	700.860us	3	3	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.510s	34.068s	237.864us	1	1	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.550s	39.157s	53.806us	3	3	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	0.760s	39.154s	177.797us	3	3	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.530s	35.128s	18.387us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.530s	35.128s	18.387us	20	20	100.00
V2S		TOTAL				22	22	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	0.600s	34.073s	100.082us	0	1	0.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	6.550s	41.140s	3.761ms	2	3	66.67
V3		TOTAL				2	4	50.00
		TOTAL				84	89	94.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	9	8	8	88.89
V3	2	2	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.09	96.65	99.62	96.00	96.40	97.45	99.01

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

  • Test pwrmgr_reset has 1 failures.

    • 0.pwrmgr_reset.25018330871265642791488524041731237895756060907524705777292480479473491184703
      Line 116, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_reset/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 0.pwrmgr_disable_rom_integrity_check.28895333289717031210345812455269261450299480763151734541438211126621531007766
      Line 169, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '((!clk_en) || status)' has 1 failures:

  • Test pwrmgr_escalation_timeout has 1 failures.

    • 0.pwrmgr_escalation_timeout.46478308689727712874214581490363734307004734490394357625919557917039596662416
      Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

            Offending '((!clk_en) || status)'
        UVM_ERROR @ 100081858 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
        UVM_INFO @ 100081858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_base_vseq.sv:607) [pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 1.pwrmgr_stress_all_with_rand_reset.70326777379362940389143809872695010731167723330006676647022590794292732071465
      Line 2885, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3760775836 ps: (pwrmgr_base_vseq.sv:607) [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] timeout waiting for pwrmgr fast fsm target activity
        UVM_INFO @ 3760775836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 2.pwrmgr_reset_invalid.113316073542794628791633428729126518676079292682606663368533354496608918086783
      Line 99, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/2.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  59798340 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitLowPower
        UVM_INFO @  59798340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---