RACL_CTRL Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	racl_ctrl_smoke	0.490s	30.174s	24.778us	1	1	100.00
V1	csr_hw_reset	racl_ctrl_csr_hw_reset	0.510s	36.121s	29.419us	5	5	100.00
V1	csr_rw	racl_ctrl_csr_rw	0.540s	56.227s	38.727us	20	20	100.00
V1	csr_bit_bash	racl_ctrl_csr_bit_bash	1.560s	35.111s	436.973us	5	5	100.00
V1	csr_aliasing	racl_ctrl_csr_aliasing	0.570s	44.126s	175.682us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	racl_ctrl_csr_mem_rw_with_rand_reset	0.850s	53.188s	183.749us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	racl_ctrl_csr_rw	0.540s	56.227s	38.727us	20	20	100.00
		racl_ctrl_csr_aliasing	0.570s	44.126s	175.682us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	error_log	error_log				0	0	--
V2	alert_test	racl_ctrl_alert_test	0.530s	36.121s	79.671us	4	4	100.00
V2	intr_test	racl_ctrl_intr_test	0.540s	48.133s	22.371us	49	50	98.00
V2	tl_d_oob_addr_access	racl_ctrl_tl_errors	1.220s	48.143s	42.496us	20	20	100.00
V2	tl_d_illegal_access	racl_ctrl_tl_errors	1.220s	48.143s	42.496us	20	20	100.00
V2	tl_d_outstanding_access	racl_ctrl_csr_hw_reset	0.510s	36.121s	29.419us	5	5	100.00
		racl_ctrl_csr_rw	0.540s	56.227s	38.727us	20	20	100.00
		racl_ctrl_csr_aliasing	0.570s	44.126s	175.682us	5	5	100.00
		racl_ctrl_same_csr_outstanding	0.570s	34.079s	26.321us	3	3	100.00
V2	tl_d_partial_access	racl_ctrl_csr_hw_reset	0.510s	36.121s	29.419us	5	5	100.00
		racl_ctrl_csr_rw	0.540s	56.227s	38.727us	20	20	100.00
		racl_ctrl_csr_aliasing	0.570s	44.126s	175.682us	5	5	100.00
		racl_ctrl_same_csr_outstanding	0.570s	34.079s	26.321us	3	3	100.00
V2		TOTAL				76	77	98.70
V2S	tl_intg_err	racl_ctrl_tl_intg_err	0.900s	36.117s	236.534us	4	4	100.00
		racl_ctrl_sec_cm				0	0	--
V2S		TOTAL				4	4	100.00
V3	stress_all_with_rand_reset	racl_ctrl_stress_all_with_rand_reset	25.220s	59.217s	45.100ms	4	4	100.00
V3		TOTAL				4	4	100.00
	Unmapped tests	racl_ctrl_stress_all	0.560s	35.162s	152.551us	1	1	100.00
		TOTAL				141	142	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	5	4	3	60.00
V2S	2	1	1	50.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.89	98.93	88.35	99.41	--	96.68	96.07	77.91

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:824) [racl_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (* [*] vs * [*]) has 1 failures:
  • Test racl_ctrl_intr_test has 1 failures.

    • 10.racl_ctrl_intr_test.44604590226729068587666756207868785572084947780008424970885840711887392288123
      Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/racl_ctrl_top_dragonfly-sim-vcs/10.racl_ctrl_intr_test/latest/run.log

        UVM_ERROR @  13616933 ps: (cip_base_vseq.sv:824) [uvm_test_top.env.virtual_sequencer.racl_ctrl_common_vseq] Check failed exp_intr_pin === act_intr_pin (0x0 [0] vs 0x1 [1])
        UVM_INFO @  13616933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---