ROM_CTRL/32KB Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.490s	4.287m	377.375us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.780s	53.091s	305.914us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.350s	50.083s	301.591us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.240s	51.076s	543.250us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	4.230s	51.076s	126.154us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	5.740s	40.129s	617.193us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.350s	50.083s	301.591us	20	20	100.00
		rom_ctrl_csr_aliasing	4.230s	51.076s	126.154us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.170s	1.151m	128.322us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.780s	56.099s	166.253us	5	5	100.00
V1		TOTAL				67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.230s	4.053m	184.893us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	24.280s	3.953m	7.980ms	5	5	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.170s	2.002m	2.051ms	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	4.950s	2.919m	164.615us	3	3	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	10.140s	1.435m	982.126us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	10.140s	1.435m	982.126us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.780s	53.091s	305.914us	5	5	100.00
		rom_ctrl_csr_rw	4.350s	50.083s	301.591us	20	20	100.00
		rom_ctrl_csr_aliasing	4.230s	51.076s	126.154us	5	5	100.00
		rom_ctrl_same_csr_outstanding	4.950s	52.079s	387.057us	3	3	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.780s	53.091s	305.914us	5	5	100.00
		rom_ctrl_csr_rw	4.350s	50.083s	301.591us	20	20	100.00
		rom_ctrl_csr_aliasing	4.230s	51.076s	126.154us	5	5	100.00
		rom_ctrl_same_csr_outstanding	4.950s	52.079s	387.057us	3	3	100.00
V2		TOTAL				35	35	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	23.100s	2.136m	1.548ms	3	3	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.581m	5.807m	1.153ms	5	5	100.00
		rom_ctrl_tl_intg_err	41.080s	1.803m	515.952us	7	7	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.581m	5.807m	1.153ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.581m	5.807m	1.153ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.581m	5.807m	1.153ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.581m	5.807m	1.153ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.490s	4.287m	377.375us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.490s	4.287m	377.375us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.490s	4.287m	377.375us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	41.080s	1.803m	515.952us	7	7	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
		rom_ctrl_kmac_err_chk	11.170s	2.002m	2.051ms	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.681m	5.287m	7.257ms	3	3	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	23.100s	2.136m	1.548ms	3	3	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.581m	5.807m	1.153ms	5	5	100.00
V2S		TOTAL				18	18	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.020m	4.321m	10.198ms	3	3	100.00
V3		TOTAL				3	3	100.00
		TOTAL				123	123	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.59	98.37	95.57	100.00	100.00	96.80	99.28

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52