ROM_CTRL/64KB Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	9.150s	13.079s	4.152ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.140s	25.242s	1.370ms	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.300s	23.241s	207.027us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	11.620s	29.256s	8.218ms	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.210s	26.078s	425.544us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.780s	28.249s	293.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.300s	23.241s	207.027us	20	20	100.00
		rom_ctrl_csr_aliasing	8.210s	26.078s	425.544us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.640s	23.235s	2.390ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.000s	23.235s	1.064ms	5	5	100.00
V1		TOTAL				67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.640s	11.051s	298.111us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	22.400s	27.142s	2.760ms	3	3	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.770s	15.093s	573.624us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.040s	15.071s	1.999ms	3	3	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.050s	30.262s	297.994us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.050s	30.262s	297.994us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.140s	25.242s	1.370ms	5	5	100.00
		rom_ctrl_csr_rw	7.300s	23.241s	207.027us	20	20	100.00
		rom_ctrl_csr_aliasing	8.210s	26.078s	425.544us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.300s	25.075s	1.113ms	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.140s	25.242s	1.370ms	5	5	100.00
		rom_ctrl_csr_rw	7.300s	23.241s	207.027us	20	20	100.00
		rom_ctrl_csr_aliasing	8.210s	26.078s	425.544us	5	5	100.00
		rom_ctrl_same_csr_outstanding	11.300s	25.075s	1.113ms	20	20	100.00
V2		TOTAL				50	50	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	33.800s	44.307s	4.152ms	4	4	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	7.374m	7.442m	5.200ms	3	3	100.00
		rom_ctrl_tl_intg_err	1.577m	1.728m	1.555ms	8	8	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	7.374m	7.442m	5.200ms	3	3	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	7.374m	7.442m	5.200ms	3	3	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	7.374m	7.442m	5.200ms	3	3	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	7.374m	7.442m	5.200ms	3	3	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	9.150s	13.079s	4.152ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	9.150s	13.079s	4.152ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	9.150s	13.079s	4.152ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.577m	1.728m	1.555ms	8	8	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
		rom_ctrl_kmac_err_chk	10.770s	15.093s	573.624us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.148m	2.233m	4.787ms	3	3	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	33.800s	44.307s	4.152ms	4	4	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	7.374m	7.442m	5.200ms	3	3	100.00
V2S		TOTAL				18	18	100.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.378m	2.468m	6.791ms	5	5	100.00
V3		TOTAL				5	5	100.00
		TOTAL				140	140	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.58	99.59	98.81	95.57	100.00	100.00	96.80	99.28

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52