RSTMGR_CNSTY_CHK/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1		TOTAL				0	0	--
V2		TOTAL				0	0	--
V2S	unexpected_child_reset_activity	rstmgr_cnsty_chk_smoke				0	0	--
V2S	child_reset_asserts_late	child_reset_asserts_late				0	0	--
V2S	child_reset_releases_late	child_reset_releases_late				0	0	--
V2S	parent_reset_asserts_late	parent_reset_asserts_late				0	0	--
V2S	parent_reset_releases_late	parent_reset_releases_late				0	0	--
V2S		TOTAL				0	0	--
V3		TOTAL				0	0	--
	Unmapped tests	rstmgr_cnsty_chk_test	2.770s	41.703s	8.855ms	3	3	100.00
		TOTAL				3	3	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V2S	5	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.87	98.41	86.21	100.00	92.31	98.31	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52