RSTMGR/DRAGONFLY Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	0.830s	5.042s	58.531us	1	1	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.990s	8.147s	90.531us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.870s	7.105s	36.407us	3	3	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	2.750s	11.189s	144.429us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.170s	10.136s	50.048us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.320s	10.236s	102.925us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.870s	7.105s	36.407us	3	3	100.00
		rstmgr_csr_aliasing	1.170s	10.136s	50.048us	5	5	100.00
V1		TOTAL				22	22	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.560s	10.120s	143.732us	3	3	100.00
V2	sw_rst	rstmgr_sw_rst	0.820s	5.047s	46.292us	3	3	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	0.890s	10.082s	67.138us	3	3	100.00
V2	reset_info	rstmgr_reset	2.620s	11.097s	420.376us	1	1	100.00
V2	cpu_info	rstmgr_reset	2.620s	11.097s	420.376us	1	1	100.00
V2	alert_info	rstmgr_reset	2.620s	11.097s	420.376us	1	1	100.00
V2	reset_info_capture	rstmgr_reset	2.620s	11.097s	420.376us	1	1	100.00
V2	stress_all	rstmgr_stress_all	22.350s	26.393s	4.218ms	4	4	100.00
V2	alert_test	rstmgr_alert_test	0.990s	10.116s	38.429us	3	3	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	1.820s	11.147s	45.467us	4	4	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	1.820s	11.147s	45.467us	4	4	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.990s	8.147s	90.531us	5	5	100.00
		rstmgr_csr_rw	0.870s	7.105s	36.407us	3	3	100.00
		rstmgr_csr_aliasing	1.170s	10.136s	50.048us	5	5	100.00
		rstmgr_same_csr_outstanding	1.130s	9.245s	40.123us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.990s	8.147s	90.531us	5	5	100.00
		rstmgr_csr_rw	0.870s	7.105s	36.407us	3	3	100.00
		rstmgr_csr_aliasing	1.170s	10.136s	50.048us	5	5	100.00
		rstmgr_same_csr_outstanding	1.130s	9.245s	40.123us	20	20	100.00
V2		TOTAL				41	41	100.00
V2S	tl_intg_err	rstmgr_sec_cm	13.460s	21.258s	3.681ms	3	3	100.00
		rstmgr_tl_intg_err	3.390s	13.156s	709.174us	7	7	100.00
V2S	prim_count_check	rstmgr_sec_cm	13.460s	21.258s	3.681ms	3	3	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	13.460s	21.258s	3.681ms	3	3	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.390s	13.156s	709.174us	7	7	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.130s	10.112s	66.250us	3	3	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	3.880s	12.172s	455.548us	6	6	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	2.290s	11.127s	291.220us	4	4	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	13.460s	21.258s	3.681ms	3	3	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.870s	7.105s	36.407us	3	3	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.870s	7.105s	36.407us	3	3	100.00
V2S		TOTAL				23	23	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				86	86	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.19	99.43	100.00	--	99.72	97.62	98.49

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52