RSTMGR/EGRET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	0.900s	5.105s	188.242us	1	1	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.920s	9.212s	145.286us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.900s	10.195s	86.357us	3	3	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	3.330s	11.181s	1.158ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.750s	10.193s	351.153us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.080s	9.188s	137.650us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.900s	10.195s	86.357us	3	3	100.00
		rstmgr_csr_aliasing	1.750s	10.193s	351.153us	5	5	100.00
V1		TOTAL				22	22	100.00
V2	reset_stretcher	rstmgr_por_stretcher	0.980s	7.179s	209.323us	3	3	100.00
V2	sw_rst	rstmgr_sw_rst	1.510s	8.184s	312.528us	3	3	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	0.940s	6.060s	233.991us	3	3	100.00
V2	reset_info	rstmgr_reset	2.360s	8.130s	808.653us	1	1	100.00
V2	cpu_info	rstmgr_reset	2.360s	8.130s	808.653us	1	1	100.00
V2	alert_info	rstmgr_reset	2.360s	8.130s	808.653us	1	1	100.00
V2	reset_info_capture	rstmgr_reset	2.360s	8.130s	808.653us	1	1	100.00
V2	stress_all	rstmgr_stress_all	35.730s	41.863s	17.204ms	5	5	100.00
V2	alert_test	rstmgr_alert_test	0.670s	5.083s	85.611us	3	3	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	3.100s	8.179s	518.626us	4	4	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	3.100s	8.179s	518.626us	4	4	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.920s	9.212s	145.286us	5	5	100.00
		rstmgr_csr_rw	0.900s	10.195s	86.357us	3	3	100.00
		rstmgr_csr_aliasing	1.750s	10.193s	351.153us	5	5	100.00
		rstmgr_same_csr_outstanding	1.210s	10.272s	260.695us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.920s	9.212s	145.286us	5	5	100.00
		rstmgr_csr_rw	0.900s	10.195s	86.357us	3	3	100.00
		rstmgr_csr_aliasing	1.750s	10.193s	351.153us	5	5	100.00
		rstmgr_same_csr_outstanding	1.210s	10.272s	260.695us	20	20	100.00
V2		TOTAL				42	42	100.00
V2S	tl_intg_err	rstmgr_sec_cm	17.370s	21.384s	16.824ms	3	3	100.00
		rstmgr_tl_intg_err	2.280s	11.225s	901.748us	6	6	100.00
V2S	prim_count_check	rstmgr_sec_cm	17.370s	21.384s	16.824ms	3	3	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	17.370s	21.384s	16.824ms	3	3	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	2.280s	11.225s	901.748us	6	6	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	0.790s	5.099s	142.030us	3	3	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	5.200s	11.250s	1.973ms	5	5	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	0.840s	5.093s	300.858us	3	3	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	17.370s	21.384s	16.824ms	3	3	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.900s	10.195s	86.357us	3	3	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.900s	10.195s	86.357us	3	3	100.00
V2S		TOTAL				20	20	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				84	84	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.51	99.38	100.00	--	99.83	98.13	98.76

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52