0ff052588e| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 3.660s | 12.099s | 2.061ms | 3 | 3 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.010s | 13.084s | 482.768us | 4 | 4 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.640s | 12.072s | 342.615us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 29.270s | 39.305s | 17.086ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 4.620s | 14.120s | 2.629ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 38.450s | 42.305s | 23.660ms | 7 | 7 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 13.620s | 18.173s | 8.808ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 50.600s | 59.482s | 32.992ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 3.005m | 3.104m | 132.611ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 3.670s | 2.152m | 1.067ms | 7 | 7 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.880s | 5.049s | 232.795us | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.200s | 16.067s | 165.964us | 3 | 3 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.830s | 10.077s | 169.390us | 0 | 2 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.980s | 22.057s | 529.115us | 4 | 4 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.130s | 16.067s | 759.483us | 3 | 3 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 1.060s | 22.060s | 83.899us | 4 | 4 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 4.940s | 1.868m | 1.640ms | 8 | 8 | 100.00 |
| V1 | progbuf_busy | rv_dm_cmderr_busy | 3.670s | 2.152m | 1.067ms | 7 | 7 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.490s | 16.070s | 253.812us | 3 | 3 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 2.850s | 31.065s | 764.109us | 5 | 5 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.200s | 16.067s | 165.964us | 3 | 3 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 1.190s | 16.074s | 126.517us | 3 | 3 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.290s | 16.101s | 334.525us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.280s | 15.095s | 247.066us | 3 | 3 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 41.570s | 50.369s | 29.340ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 19.420s | 30.199s | 6.017ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 2.490s | 14.100s | 184.360us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 19.420s | 30.199s | 6.017ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.280s | 15.095s | 247.066us | 3 | 3 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 1.100s | 15.103s | 126.468us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 1.310s | 14.095s | 178.147us | 5 | 5 | 100.00 |
| V1 | TOTAL | 164 | 166 | 98.80 | ||||
| V2 | idcode | rv_dm_smoke | 3.660s | 12.099s | 2.061ms | 3 | 3 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.180s | 11.105s | 840.342us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.290s | 8.069s | 536.758us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | rv_dm_dmi_failed_op | 0.730s | 10.089s | 177.793us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.210s | 7.063s | 991.747us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 10.789m | 12.155m | 300.000ms | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 9.443m | 11.064m | 300.000ms | 0 | 20 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 10.495m | 12.082m | 300.000ms | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 12.551m | 13.769m | 300.000ms | 0 | 20 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.640s | 9.087s | 265.890us | 0 | 2 | 0.00 |
| V2 | sba_debug_disabled | rv_dm_sba_debug_disabled | 3.400s | 32.078s | 2.002ms | 5 | 5 | 100.00 |
| V2 | ndmreset_req | rv_dm_ndmreset_req | 2.110s | 18.074s | 874.682us | 3 | 3 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 1.050s | 26.054s | 92.333us | 0 | 5 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 15.970s | 29.097s | 9.151ms | 5 | 5 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 48.490s | 57.472s | 29.309ms | 6 | 6 | 100.00 | ||
| V2 | hartsel_warl | rv_dm_hartsel_warl | 0.950s | 11.103s | 86.555us | 3 | 3 | 100.00 |
| V2 | stress_all | rv_dm_stress_all | 6.960s | 1.568m | 8.817ms | 3 | 7 | 42.86 |
| V2 | alert_test | rv_dm_alert_test | 0.890s | 10.060s | 89.036us | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 3.460s | 12.097s | 884.524us | 4 | 4 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 3.460s | 12.097s | 884.524us | 4 | 4 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 19.420s | 30.199s | 6.017ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.290s | 16.101s | 334.525us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.280s | 15.095s | 247.066us | 3 | 3 | 100.00 | ||
| rv_dm_same_csr_outstanding | 5.950s | 20.133s | 506.128us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 19.420s | 30.199s | 6.017ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.290s | 16.101s | 334.525us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.280s | 15.095s | 247.066us | 3 | 3 | 100.00 | ||
| rv_dm_same_csr_outstanding | 5.950s | 20.133s | 506.128us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 43 | 134 | 32.09 | ||||
| V2S | tl_intg_err | rv_dm_sec_cm | 2.470s | 27.067s | 1.594ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.670s | 27.215s | 6.891ms | 14 | 14 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_dm_tl_intg_err | 20.670s | 27.215s | 6.891ms | 14 | 14 | 100.00 |
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.400s | 32.078s | 2.002ms | 5 | 5 | 100.00 |
| rv_dm_debug_disabled | 1.070s | 26.066s | 69.340us | 3 | 4 | 75.00 | ||
| V2S | sec_cm_lc_hw_debug_clr_intersig_mubi | sec_cm_lc_hw_debug_clr_intersig_mubi | 0 | 0 | -- | |||
| V2S | sec_cm_lc_dft_en_intersig_mubi | rv_dm_sba_debug_disabled | 3.400s | 32.078s | 2.002ms | 5 | 5 | 100.00 |
| rv_dm_debug_disabled | 1.070s | 26.066s | 69.340us | 3 | 4 | 75.00 | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | rv_dm_smoke | 3.660s | 12.099s | 2.061ms | 3 | 3 | 100.00 |
| V2S | sec_cm_dm_en_ctrl_lc_gated | rv_dm_buffered_enable | 1.230s | 11.058s | 674.294us | 3 | 3 | 100.00 |
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.030s | 30.073s | 227.934us | 5 | 5 | 100.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | rv_dm_sparse_lc_gate_fsm | 1.030s | 30.073s | 227.934us | 5 | 5 | 100.00 |
| V2S | sec_cm_exec_ctrl_mubi | rv_dm_buffered_enable | 1.230s | 11.058s | 674.294us | 3 | 3 | 100.00 |
| V2S | TOTAL | 30 | 31 | 96.77 | ||||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 58.970s | 1.073m | 4.830ms | 3 | 5 | 60.00 |
| V3 | TOTAL | 3 | 5 | 60.00 | ||||
| Unmapped tests | rv_dm_scanmode | 8.192m | 8.264m | 300.000ms | 0 | 1 | 0.00 | |
| TOTAL | 240 | 337 | 71.22 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 27 | 27 | 26 | 96.30 |
| V2 | 19 | 19 | 12 | 63.16 |
| V2S | 6 | 5 | 4 | 66.67 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 77.93 | 90.52 | 78.45 | 70.12 | 42.11 | 76.58 | 96.24 | 91.51 |
| Target | Elapsed |
|---|---|
| build | 00:07:13 |
| run | 30:46:43 |
| cov_merge | 30:47:37 |
| cov_report | 30:47:52 |
| Total | 30:47:52 |
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 81 failures:
0.rv_dm_sba_tl_access.105192688936382050258344058075378079033061437482379682884679718339848008532268
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_sba_tl_access.50498521529495038190913152227713173169678141041359992367018343241093925623505
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
0.rv_dm_delayed_resp_sba_tl_access.73833616018688424880199781688333752960481769017699192926490270368104949917267
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_delayed_resp_sba_tl_access.22208739914590827878434556988784951341916357831572444096179133491589940158968
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
0.rv_dm_bad_sba_tl_access.115235309184400358982512651604446638932543116284390970857860227620191973054780
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_bad_sba_tl_access.83851984265204917712040967210176832983873516851252809938987451475258762102608
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
0.rv_dm_autoincr_sba_tl_access.72781194791884095402204560461532289444812461330052942522207591362749560557765
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_autoincr_sba_tl_access.21712015136504966376131992036577096028832551363732568263861564909298784766415
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
0.rv_dm_scanmode.96058970308485314703705556186899355214798199601290115094577975343903716611668
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_scanmode/latest/run.log
UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 6 failures:
0.rv_dm_hart_unavail.52408005411893864337842704693902348517073799350206496214290055502672503695776
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 94601107 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 94601107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_hart_unavail.94686041321090805540695797633999110230791529622171093877835579202840889210480
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_hart_unavail/latest/run.log
UVM_ERROR @ 177855734 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 177855734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
6.rv_dm_stress_all.5712807297589723696829377342960496854275400962828801809896420245460800859280
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 126671907 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 126671907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyhalted) == 'b (* [] vs * [])` has 4 failures:
Test rv_dm_mem_tl_access_resuming has 2 failures.
0.rv_dm_mem_tl_access_resuming.78105233731273073464797243570753223373622411896417147157318537870792094677532
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 169389893 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 169389893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_mem_tl_access_resuming.49576919706175098057932563934470759012782595798995236985328671676482631252899
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_mem_tl_access_resuming/latest/run.log
UVM_ERROR @ 229415309 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 229415309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
2.rv_dm_stress_all_with_rand_reset.76508545886049040661981874639557131720700966809404454310294146876000872922378
Line 100, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 955882127 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 955882127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
4.rv_dm_stress_all.21358003682939456562528335116244245842811213480470470837663249568409173190884
Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 404243222 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyhalted) == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 404243222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 4 failures:
Test rv_dm_jtag_dmi_debug_disabled has 2 failures.
0.rv_dm_jtag_dmi_debug_disabled.112639816584383575097437515117560508716349847544770160733417750160936799917453
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 72702016 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2593227666 [0x9a918392] vs 0 [0x0])
UVM_INFO @ 72702016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_debug_disabled.110277797433313491256936218296110633792214843766636376720597738326903036597741
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 265890435 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (3783471483 [0xe183317b] vs 0 [0x0])
UVM_INFO @ 265890435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
3.rv_dm_stress_all.67223240829207149723278167226607691147250442483734242690811036184327184083127
Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6686556449 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (577096890 [0x2265ccba] vs 0 [0x0])
UVM_INFO @ 6686556449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
4.rv_dm_stress_all_with_rand_reset.19056228973735616025548245146016446024630431774908609425203001031639613190318
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1112179645 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (563546968 [0x21970b58] vs 0 [0x0])
UVM_INFO @ 1112179645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(($rose(mem_tl_d_o_i.d_valid) && (!debug_enabled)) -> mem_tl_d_o_i.d_error)' has 1 failures:
1.rv_dm_debug_disabled.100918723076185471283323927485375820775089185997271547874666645018994762847697
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/1.rv_dm_debug_disabled/latest/run.log
Offending '(($rose(mem_tl_d_o_i.d_valid) && (!debug_enabled)) -> mem_tl_d_o_i.d_error)'
UVM_ERROR @ 141746958 ps: (rv_dm_enable_checker.sv:46) [ASSERT FAILED] MemTLResponseWithoutDebugIsError_A
UVM_INFO @ 141746958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes has 1 failures:
5.rv_dm_stress_all.94482832530251146054029532838247822840342819812836606215906659168122312849640
Log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_dmi_interface-sim-vcs/5.rv_dm_stress_all/latest/run.log
Job timed out after 180 minutes