RV_DM/USE_JTAG_INTERFACE Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	6.920s	13.076s	1.915ms	3	3	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.240s	11.285s	648.861us	3	3	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	2.600s	13.072s	695.399us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	23.840s	29.237s	15.915ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	2.820s	12.333s	802.473us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	14.420s	19.642s	10.429ms	3	3	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	7.030s	15.087s	6.639ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.579m	2.642m	112.545ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	3.054m	3.165m	223.079ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	2.080s	31.069s	1.189ms	4	4	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.100s	32.118s	326.043us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.130s	35.071s	286.831us	3	3	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.170s	38.071s	134.273us	4	4	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.790s	37.067s	472.182us	4	4	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.990s	41.090s	1.351ms	3	3	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.220s	37.071s	122.849us	4	4	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.680s	35.072s	1.006ms	4	4	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	2.080s	31.069s	1.189ms	4	4	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.080s	11.079s	89.537us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.320s	16.068s	458.181us	3	3	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.130s	35.071s	286.831us	3	3	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.110s	26.060s	172.007us	4	4	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.830s	11.121s	119.294us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	1.670s	10.115s	221.829us	3	3	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	38.220s	45.582s	26.518ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	33.870s	42.327s	4.250ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	1.620s	12.127s	181.283us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	33.870s	42.327s	4.250ms	5	5	100.00
		rv_dm_csr_rw	1.670s	10.115s	221.829us	3	3	100.00
V1	mem_walk	rv_dm_mem_walk	0.760s	10.070s	128.583us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.850s	9.317s	66.124us	5	5	100.00
V1		TOTAL				152	152	100.00
V2	idcode	rv_dm_smoke	6.920s	13.076s	1.915ms	3	3	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	2.760s	36.077s	618.864us	4	4	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.090s	26.077s	105.389us	3	3	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.930s	27.066s	449.211us	4	4	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.570s	12.070s	954.903us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	10.028m	11.806m	300.000ms	0	20	0.00
		rv_dm_delayed_resp_sba_tl_access	10.329m	13.122m	300.000ms	0	20	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	9.395m	10.854m	300.000ms	0	20	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	10.643m	10.901m	300.000ms	0	20	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.780s	1.501m	723.480us	5	5	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	10.120s	2.102m	3.130ms	7	7	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.820s	1.885m	833.407us	6	6	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.450s	1.451m	241.821us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	20.030s	2.035m	6.657ms	7	7	100.00
		rv_dm_tap_fsm_rand_reset	52.600s	1.052m	10.026ms	6	6	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.920s	10.068s	61.509us	1	1	100.00
V2	stress_all	rv_dm_stress_all	17.720s	3.638m	6.996ms	18	18	100.00
V2	alert_test	rv_dm_alert_test	0.950s	10.065s	42.024us	3	3	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	4.190s	13.077s	1.914ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	4.190s	13.077s	1.914ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	33.870s	42.327s	4.250ms	5	5	100.00
		rv_dm_csr_hw_reset	1.830s	11.121s	119.294us	5	5	100.00
		rv_dm_csr_rw	1.670s	10.115s	221.829us	3	3	100.00
		rv_dm_same_csr_outstanding	5.120s	15.150s	562.370us	3	3	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	33.870s	42.327s	4.250ms	5	5	100.00
		rv_dm_csr_hw_reset	1.830s	11.121s	119.294us	5	5	100.00
		rv_dm_csr_rw	1.670s	10.115s	221.829us	3	3	100.00
		rv_dm_same_csr_outstanding	5.120s	15.150s	562.370us	3	3	100.00
V2		TOTAL				94	174	54.02
V2S	tl_intg_err	rv_dm_sec_cm	5.460s	14.079s	2.710ms	3	3	100.00
		rv_dm_tl_intg_err	14.820s	23.158s	5.385ms	11	11	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	14.820s	23.158s	5.385ms	11	11	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	10.120s	2.102m	3.130ms	7	7	100.00
		rv_dm_debug_disabled	1.020s	10.076s	210.585us	2	2	100.00
V2S	sec_cm_lc_hw_debug_clr_intersig_mubi	sec_cm_lc_hw_debug_clr_intersig_mubi				0	0	--
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	10.120s	2.102m	3.130ms	7	7	100.00
		rv_dm_debug_disabled	1.020s	10.076s	210.585us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	6.920s	13.076s	1.915ms	3	3	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	2.820s	1.802m	626.299us	6	6	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.490s	1.451m	247.215us	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.490s	1.451m	247.215us	5	5	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	2.820s	1.802m	626.299us	6	6	100.00
V2S		TOTAL				27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.082m	2.235m	9.485ms	10	10	100.00
V3		TOTAL				10	10	100.00
	Unmapped tests	rv_dm_scanmode	0.860s	10.071s	17.395us	1	1	100.00
		TOTAL				284	364	78.02

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	27	100.00
V2	19	19	15	78.95
V2S	6	5	5	83.33
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
80.42	95.54	90.07	69.67	87.80	88.55	95.39	35.91

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 80 failures:
  • Test rv_dm_sba_tl_access has 20 failures.

    • 0.rv_dm_sba_tl_access.3687063236963131665222949633859828880240239622764035968094174990940721931734
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_sba_tl_access.106817747666060137935039858887434022753449930857647730232198215365040530903525
      Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_delayed_resp_sba_tl_access has 20 failures.

    • 0.rv_dm_delayed_resp_sba_tl_access.16826626751378676552035259143579304835325158106195813987107324499264095738304
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_delayed_resp_sba_tl_access.40763762348091186378035211447939181560517887786836172567358592940880053209688
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_bad_sba_tl_access has 20 failures.

    • 0.rv_dm_bad_sba_tl_access.4067229225050248021536552771737211863446575092712356652778636910977444744998
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_bad_sba_tl_access.24099419975069728777317077370653273508212602237922656726489893026373916144935
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

  • Test rv_dm_autoincr_sba_tl_access has 20 failures.

    • 0.rv_dm_autoincr_sba_tl_access.61130064330809093468262068360151086171155285578159940926812219951987924803966
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rv_dm_autoincr_sba_tl_access.95461728359270179247687926133375871277579038519544831844879191520928111130445
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/rv_dm_use_jtag_interface-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log

        UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.