RV_TIMER Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.100s	19.097s	545.617us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.540s	9.087s	40.146us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	0.600s	9.084s	12.818us	3	3	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.870s	11.074s	295.249us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.590s	9.065s	34.357us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.710s	6.057s	37.651us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.600s	9.084s	12.818us	3	3	100.00
		rv_timer_csr_aliasing	0.590s	9.065s	34.357us	5	5	100.00
V1		TOTAL				22	22	100.00
V2	random_reset	rv_timer_random_reset	0.940s	14.072s	300.934us	0	1	0.00
V2	disabled	rv_timer_disabled	0.980s	16.082s	740.685us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.105m	5.360m	1.324s	3	3	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.105m	5.360m	1.324s	3	3	100.00
V2	stress	rv_timer_stress_all	0.740s	11.062s	148.978us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.730s	30.087s	33.225us	3	3	100.00
V2	intr_test	rv_timer_intr_test	0.620s	10.051s	14.274us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.880s	10.088s	864.168us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.880s	10.088s	864.168us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.540s	9.087s	40.146us	5	5	100.00
		rv_timer_csr_rw	0.600s	9.084s	12.818us	3	3	100.00
		rv_timer_csr_aliasing	0.590s	9.065s	34.357us	5	5	100.00
		rv_timer_same_csr_outstanding	0.660s	9.086s	43.310us	3	3	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.540s	9.087s	40.146us	5	5	100.00
		rv_timer_csr_rw	0.600s	9.084s	12.818us	3	3	100.00
		rv_timer_csr_aliasing	0.590s	9.065s	34.357us	5	5	100.00
		rv_timer_same_csr_outstanding	0.660s	9.086s	43.310us	3	3	100.00
V2		TOTAL				81	82	98.78
V2S	tl_intg_err	rv_timer_sec_cm	1.110s	30.097s	577.794us	3	3	100.00
		rv_timer_tl_intg_err	1.010s	9.069s	301.347us	3	3	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.010s	9.069s	301.347us	3	3	100.00
V2S		TOTAL				6	6	100.00
V3	min_value	rv_timer_min	0.680s	18.085s	75.847us	1	3	33.33
V3	max_value	rv_timer_max	0.830s	30.104s	175.560us	2	4	50.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	38.710s	1.205m	9.240ms	5	6	83.33
V3		TOTAL				8	13	61.54
		TOTAL				117	123	95.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	7	87.50
V2S	2	2	2	100.00
V3	3	3	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.91	100.00	100.00	78.66	--	100.00	96.82	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 3 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.103841725579549716886296957245253533025323665076400830128319530771190576093797
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 300934402 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x988f5904) == 0x1
        UVM_INFO @ 300934402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_min has 2 failures.

    • 1.rv_timer_min.25869500469727516131637617907934985844303042653846409628223818441915307689801
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_min/latest/run.log

        UVM_FATAL @  75846972 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa8c31d04) == 0x1
        UVM_INFO @  75846972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.rv_timer_min.76089423140717848514223887918698208308586618922200770189208056802987796806803
      Line 77, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/2.rv_timer_min/latest/run.log

        UVM_FATAL @  70173950 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x66f0f504) == 0x1
        UVM_INFO @  70173950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 2 failures:

  • Test rv_timer_max has 2 failures.

    • 1.rv_timer_max.88428401698673754153809154091098523506331679582609468691107842475644599003426
      Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/1.rv_timer_max/latest/run.log

        UVM_ERROR @ 174475888 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 174475888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.rv_timer_max.56004690257887860102638829495273686834220968640523534130446971130065996764602
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/3.rv_timer_max/latest/run.log

        UVM_ERROR @ 175560396 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 175560396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1171) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 4.rv_timer_stress_all_with_rand_reset.4851883820061324818862990648990002540308474730432885512121765382097991039371
      Line 130, in log /home/runner/_work/pavona/pavona/scratch/main/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 796224135 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 796224135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---