SPI_DEVICE/1R1W Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: `0ff052588e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	26.430s	30.376s	11.017ms	0	7	0.00
V1	csr_hw_reset	spi_device_csr_hw_reset	0.890s	5.068s	226.079us	3	3	100.00
V1	csr_rw	spi_device_csr_rw	1.540s	10.161s	320.015us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	18.790s	23.325s	5.403ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.900s	15.244s	4.267ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.220s	10.122s	606.088us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.540s	10.161s	320.015us	20	20	100.00
		spi_device_csr_aliasing	10.900s	15.244s	4.267ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.580s	9.089s	15.435us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.530s	8.123s	205.874us	5	5	100.00
V1		TOTAL				63	70	90.00
V2	csb_read	spi_device_csb_read	0.580s	7.096s	34.930us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.790s	9.125s	5.988us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.540s	5.062s	3.334us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.650s	5.083s	5.868us	0	1	0.00
V2	tpm_write	spi_device_tpm_rw	0.650s	5.083s	5.868us	0	1	0.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.360s	8.114s	2.838ms	1	1	100.00
		spi_device_tpm_sts_read	0.540s	5.061s	35.191us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.590s	5.061s	12.501us	0	1	0.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.840s	6.095s	711.528us	1	1	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.380s	6.095s	3.637ms	1	1	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.380s	6.095s	3.637ms	1	1	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	cmd_info_slots	spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	cmd_read_status	spi_device_intercept	15.640s	21.206s	7.447ms	4	4	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	cmd_read_jedec	spi_device_intercept	15.640s	21.206s	7.447ms	4	4	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	cmd_read_sfdp	spi_device_intercept	15.640s	21.206s	7.447ms	4	4	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	cmd_fast_read	spi_device_intercept	15.640s	21.206s	7.447ms	4	4	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	cmd_read_pipeline	spi_device_intercept	15.640s	21.206s	7.447ms	4	4	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	flash_cmd_upload	spi_device_upload	1.690s	6.094s	358.343us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.390s	8.110s	155.049us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.390s	8.110s	155.049us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.390s	8.110s	155.049us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	20.820s	29.331s	3.321ms	1	6	16.67
		spi_device_read_buffer_direct	2.880s	12.139s	588.007us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.390s	8.110s	155.049us	1	1	100.00
		spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	quad_spi	spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	dual_spi	spi_device_flash_all	33.490s	37.419s	12.148ms	1	7	14.29
V2	4b_3b_feature	spi_device_cfg_cmd	7.580s	12.139s	1.693ms	0	1	0.00
V2	write_enable_disable	spi_device_cfg_cmd	7.580s	12.139s	1.693ms	0	1	0.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	26.430s	30.376s	11.017ms	0	7	0.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.680s	16.168s	10.171ms	0	8	0.00
V2	stress_all	spi_device_stress_all	8.210s	17.170s	8.653ms	0	17	0.00
V2	alert_test	spi_device_alert_test	0.580s	7.065s	31.200us	3	3	100.00
V2	intr_test	spi_device_intr_test	0.700s	9.142s	29.400us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.220s	11.127s	583.664us	5	5	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.220s	11.127s	583.664us	5	5	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	0.890s	5.068s	226.079us	3	3	100.00
		spi_device_csr_rw	1.540s	10.161s	320.015us	20	20	100.00
		spi_device_csr_aliasing	10.900s	15.244s	4.267ms	5	5	100.00
		spi_device_same_csr_outstanding	2.400s	8.099s	3.712ms	3	3	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	0.890s	5.068s	226.079us	3	3	100.00
		spi_device_csr_rw	1.540s	10.161s	320.015us	20	20	100.00
		spi_device_csr_aliasing	10.900s	15.244s	4.267ms	5	5	100.00
		spi_device_same_csr_outstanding	2.400s	8.099s	3.712ms	3	3	100.00
V2		TOTAL				75	135	55.56
V2S	tl_intg_err	spi_device_sec_cm	0.990s	8.079s	307.173us	3	3	100.00
		spi_device_tl_intg_err	12.610s	19.254s	2.207ms	6	6	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.610s	19.254s	2.207ms	6	6	100.00
V2S		TOTAL				9	9	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
	Unmapped tests	spi_device_flash_mode_ignore_cmds	49.250s	57.754s	17.406ms	0	8	0.00
		TOTAL				147	222	66.22

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	8	8	7	87.50
V2	22	22	13	59.09
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
71.80	95.48	90.58	70.75	44.68	94.76	87.03	19.30

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.90725148780880043241217129823254849958452047920818014972300421153948291973547
Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   1241350 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[69])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   1241350 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   1241350 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[965])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.70529187302046818907774583881037938850156099702830625964736506079011335377160
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   6765214 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[79])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   6765214 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   6765214 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_FATAL (spi_device_scoreboard.sv:2474) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 15 failures:
- Test spi_device_flash_and_tpm_min_idle has 3 failures.
  - 0.spi_device_flash_and_tpm_min_idle.46711607089269303528550536948429005048323810918344484895282246832172464952856
    Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @   4906369 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @   4906369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.spi_device_flash_and_tpm_min_idle.11670171358004993969171554773361421216204409994953146209187398030600336243421
    Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_FATAL @  10949389 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  10949389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test spi_device_stress_all has 9 failures.
  - 0.spi_device_stress_all.11168539034657540824993409615269675197413293195875091344428475659386598252424
    Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 427995766 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 427995766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.spi_device_stress_all.112037635621316837742007571801611308189773365375688415457687547594222608312267
    Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest/run.log
```
  UVM_FATAL @ 2621133742 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2621133742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
- Test spi_device_flash_and_tpm has 3 failures.
  - 2.spi_device_flash_and_tpm.41905630498696114193336212213435718627073964219495381726490034025395854740626
    Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest/run.log
```
  UVM_FATAL @ 301524124 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 301524124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.spi_device_flash_and_tpm.51718962996412861526121415275415636229430988843290508246515502368257464458270
    Line 87, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log
```
  UVM_FATAL @  42852363 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  42852363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2132) [scoreboard] Check failed (spi_mem.addr_exists(csr_addr)) has 14 failures:

Test spi_device_tpm_all has 1 failures.

0.spi_device_tpm_all.66152447336258440896966524551424872928149212748372936572396173194970817467869
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest/run.log

  UVM_ERROR @   2890687 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @   2980687 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_FATAL @  12500687 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @  12500687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm has 2 failures.

0.spi_device_flash_and_tpm.82820933425276419421349212266258228882512768035767899137258423822438599255326
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 106587196 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 106597196 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 106627196 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 106637196 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 106667196 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))

1.spi_device_flash_and_tpm.100831307333075549644946069057038602322976949599519384306176265627514757421703
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 203938295 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 203948933 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_FATAL @ 1465562543 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 1465562543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test spi_device_flash_and_tpm_min_idle has 3 failures.

1.spi_device_flash_and_tpm_min_idle.11855332569979526858485135887285134479205345583764670120993453487198438815567
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 4752328148 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 4752369815 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 4753203155 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 4753244822 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_FATAL @ 10171246499 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])

4.spi_device_flash_and_tpm_min_idle.55171825601038690793532543764820605754165656930779776744905043284829195835026
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @  25458379 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @  25540011 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @  25886947 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @  25927763 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @  26213475 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))

... and 1 more failures.

Test spi_device_stress_all has 8 failures.

1.spi_device_stress_all.108280862489978641521633253833411633376752015513683972451136012549435720206406
Line 98, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 213785674 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 213838306 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_FATAL @ 8652905818 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 8652905818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.spi_device_stress_all.80414139186954175720279316344355950849400386245260904580940241336001175961215
Line 93, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest/run.log

  UVM_ERROR @ 126925214 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 126955214 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 127225214 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 127235214 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 127495214 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))

... and 6 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2210) [scoreboard] Check failed item.d_data[TL_DW-*] == tl_ul_side_addr_mode_pending (* [*] vs * [*]) Comparison mismatch [pending], act (*) != exp * has 11 failures:

Test spi_device_cfg_cmd has 1 failures.

0.spi_device_cfg_cmd.70661910160549583610085639235861606378874938559518711163610166572449815814846
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest/run.log

  UVM_ERROR @ 155505466 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 289165993 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_INFO @ 289165993 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x6
  UVM_ERROR @ 418138870 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 547174249 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1

Test spi_device_flash_mode_ignore_cmds has 5 failures.

0.spi_device_flash_mode_ignore_cmds.58783961313794704721182841622164575589907488600695987600456796220038099829563
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 398830237 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 2118260659 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 2642639854 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 2955975694 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 4483487914 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (1 [0x1] vs 0 [0x0]) Comparison mismatch [addr_4b_en], act (0x1) != exp          0

4.spi_device_flash_mode_ignore_cmds.17569049487151071339183646260279707926771436126984698602129585263090295005420
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @  76974405 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @  98995943 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 128496887 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 293418831 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 294127187 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf5350e) != exp '{'{other_status:'h3d4d43, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h628b9, wel:'h0, busy:'h0}, '{other_status:'h3d4d43, wel:'h0, busy:'h0}}

... and 3 more failures.

Test spi_device_flash_all has 1 failures.

3.spi_device_flash_all.55596291943919098017542115522890399903736144793635880406741874275119749519589
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 262347348 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 303560058 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (0 [0x0] vs 1 [0x1]) Comparison mismatch [addr_4b_en], act (0x0) != exp          1
  UVM_ERROR @ 303560058 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 303560058 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.addr_mode.addr_4b_en reset value: 0x0
  UVM_ERROR @ 305151663 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (0 [0x0] vs 1 [0x1]) Comparison mismatch [addr_4b_en], act (0x0) != exp          1

Test spi_device_flash_and_tpm has 2 failures.

5.spi_device_flash_and_tpm.26730053687640816431901136670266160691515443832647679916372357010804021999465
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 449626392 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 2548847453 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 2548847453 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare CmdFifoNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 2548902249 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (129 [0x81] vs 0 [0x0]) CSR upload_status compare mismatch act 0x81 != exp 0x0
  UVM_ERROR @ 2549039239 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1 [0x1] vs 0 [0x0]) CSR upload_status2 compare mismatch act 0x1 != exp 0x0

6.spi_device_flash_and_tpm.42040465359859141873014099746098640000168326937078413754902761286848301511496
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 203803151 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 224863736 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 224894039 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 1204347605 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @ 1204438514 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))

Test spi_device_flash_and_tpm_min_idle has 2 failures.

5.spi_device_flash_and_tpm_min_idle.38949744024995345546097079703722374651133137876770899902325930097183400119467
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 433370826 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_FATAL @ 445696839 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 445696839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.spi_device_flash_and_tpm_min_idle.69346005758596566563917678014428501468257826243155424309379108210694625505994
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 260735799 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 742719972 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 786065109 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 786679712 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (1 [0x1] vs 0 [0x0]) Comparison mismatch [addr_4b_en], act (0x1) != exp          0
  UVM_ERROR @ 786679712 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1

UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 4 failures:

Test spi_device_flash_mode has 4 failures.

1.spi_device_flash_mode.70262299108965493827397739564276905012283358287412211089856652562332803486679
Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 697779245 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (4 [0x4] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x4 != exp 0x0
  UVM_ERROR @ 1219525071 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @ 1279988873 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_ERROR @ 1585165003 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @ 1645700233 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0

2.spi_device_flash_mode.83796942275273545753205014925685191707762687233473973808513387722558369576886
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest/run.log

  UVM_ERROR @  42582762 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1 [0x1] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x1 != exp 0x0
  UVM_ERROR @  43518950 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (5 [0x5] vs 1 [0x1]) CSR last_read_addr compare mismatch act 0x5 != exp 0x1
  UVM_ERROR @  52838276 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @  61008644 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_ERROR @  72796102 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0

... and 2 more failures.

UVM_ERROR (spi_device_scoreboard.sv:2206) [scoreboard] Check failed item.d_data[*] == exp_addr_mode (* [*] vs * [*]) Comparison mismatch [addr_4b_en], act (*) != exp * has 2 failures:

Test spi_device_flash_all has 1 failures.

0.spi_device_flash_all.69807502979181220413693545623087232008502361552758516964914729838792220980272
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 463690896 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (1 [0x1] vs 0 [0x0]) Comparison mismatch [addr_4b_en], act (0x1) != exp          0
  UVM_ERROR @ 463690896 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 463690896 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: spi_device_reg_block.addr_mode.addr_4b_en reset value: 0x0
  UVM_ERROR @ 543024864 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d8aa) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3e77fb, wel:'h0, busy:'h0}, '{other_status:'h2362a, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1040612178 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d8aa) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3e77fb, wel:'h0, busy:'h0}, '{other_status:'h2362a, wel:'h0, busy:'h0}}

Test spi_device_flash_mode_ignore_cmds has 1 failures.

2.spi_device_flash_mode_ignore_cmds.40229416269334331136088615378059229558632537408506364741909546300746635402058
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 3506736664 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (0 [0x0] vs 1 [0x1]) Comparison mismatch [addr_4b_en], act (0x0) != exp          1
  UVM_ERROR @ 3506736664 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 3506736664 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.addr_mode.addr_4b_en reset value: 0x0
  UVM_ERROR @ 12686776664 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (0 [0x0] vs 1 [0x1]) Comparison mismatch [addr_4b_en], act (0x0) != exp          1
  UVM_ERROR @ 12686776664 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1

UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 2 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

1.spi_device_flash_mode_ignore_cmds.77598988371262411805076272245370062911011918336499513766719620538663359610029
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @ 1670178058 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfa42b6) != exp '{'{other_status:'h3e90ad, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3e90ad, wel:'h0, busy:'h0}}
  UVM_ERROR @ 1670344730 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 1670459317 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfa42b6) != exp '{'{other_status:'h3e90ad, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3e90ad, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3346762957 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfa42b6) != exp '{'{other_status:'h3e90ad, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3e90ad, wel:'h0, busy:'h0}}
  UVM_ERROR @ 3347221305 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xfa42b6) != exp '{'{other_status:'h3e90ad, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3e90ad, wel:'h0, busy:'h0}, '{other_status:'h1dcc2a, wel:'h0, busy:'h0}}

Test spi_device_flash_all has 1 failures.

1.spi_device_flash_all.67972218151612119696020833764625915670541665998475531132329630421044126354274
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 128317015 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xa9c90e) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h2a7243, wel:'h0, busy:'h0}, '{other_status:'h218b0a, wel:'h0, busy:'h0}}
  UVM_ERROR @ 511358219 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @ 1357541557 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x731bba) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h23584c, wel:'h0, busy:'h0}, '{other_status:'h1cc6ee, wel:'h0, busy:'h0}}
  UVM_INFO @ 2373363983 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/8
  UVM_INFO @ 2373363983 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 1/8

UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadNotEmpty mismatch, act (*) != exp * has 2 failures:

Test spi_device_flash_all has 2 failures.

5.spi_device_flash_all.40495909004859338543606129450842882619746166069272789521270956369832198812429
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 263270588 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 263270588 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare CmdFifoNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 263576708 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (129 [0x81] vs 0 [0x0]) CSR upload_status compare mismatch act 0x81 != exp 0x0
  UVM_ERROR @ 263637932 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (159 [0x9f] vs 0 [0x0]) CSR upload_status2 compare mismatch act 0x9f != exp 0x0
  UVM_ERROR @ 263944052 ps: (spi_device_scoreboard.sv:2438) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size > 0 (0 [0x0] vs 0 [0x0])

6.spi_device_flash_all.109192270356057059228208633081822977097292037056412808540389643912799372145237
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 464885971 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 464885971 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare CmdFifoNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 464990136 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (33153 [0x8181] vs 0 [0x0]) CSR upload_status compare mismatch act 0x8181 != exp 0x0
  UVM_ERROR @ 465115134 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (3 [0x3] vs 0 [0x0]) CSR upload_status2 compare mismatch act 0x3 != exp 0x0
  UVM_ERROR @ 465302631 ps: (spi_device_scoreboard.sv:2438) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size > 0 (0 [0x0] vs 0 [0x0])

UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.68138940062852459070505102298751692348066386656435727463191676705863134073383
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @   1002508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6c1022 [11011000001000000100010] vs 0x0 [0])
  UVM_ERROR @   1060508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b1f11 [1010110001111100010001] vs 0x0 [0])
  UVM_ERROR @   1103508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x24a5cd [1001001010010111001101] vs 0x0 [0])
  UVM_ERROR @   1109508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3eab63 [1111101010101101100011] vs 0x0 [0])
  UVM_ERROR @   1112508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x87f81c [100001111111100000011100] vs 0x0 [0])

UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare TpmHeaderNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_tpm_rw has 1 failures.

0.spi_device_tpm_rw.23577734459537847452492043704798832083583927684990788113417561265200005074055
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest/run.log

  UVM_ERROR @   1131539 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare TpmHeaderNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @   4724942 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare TpmHeaderNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @   4779887 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @   4790876 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
  UVM_ERROR @   4823843 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))

UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_mode has 1 failures.

0.spi_device_flash_mode.32877606598109143989329336243744932796916812406543526795636072999410554385715
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest/run.log

  UVM_ERROR @ 1457594294 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @ 1529454294 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
  UVM_ERROR @ 1864974294 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1372 [0x55c] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x55c != exp 0x0
  UVM_ERROR @ 2519414294 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
  UVM_ERROR @ 2591574294 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0

UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadOverflow mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_all has 1 failures.

2.spi_device_flash_all.101122734188663471438401797176227835343707212426882698420587443114716686080065
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 134720289 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadOverflow mismatch, act (0x1) != exp 0
  UVM_ERROR @ 134720289 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 134720289 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare CmdFifoNotEmpty mismatch, act (0x1) != exp 0
  UVM_ERROR @ 134800289 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (33153 [0x8181] vs 0 [0x0]) CSR upload_status compare mismatch act 0x8181 != exp 0x0
  UVM_ERROR @ 134880289 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (256 [0x100] vs 0 [0x0]) CSR upload_status2 compare mismatch act 0x100 != exp 0x0

UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_mode_ignore_cmds has 1 failures.

3.spi_device_flash_mode_ignore_cmds.77326259311999830470469143430791827636413840370152328068534685229952854809710
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest/run.log

  UVM_ERROR @  99164917 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @  99354917 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
  UVM_ERROR @  99464917 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 102874917 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
  UVM_ERROR @ 102964917 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}