0ff052588e| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_device_flash_and_tpm | 5.490s | 10.110s | 4.166ms | 0 | 16 | 0.00 |
| V1 | csr_hw_reset | spi_device_csr_hw_reset | 0.940s | 10.094s | 51.475us | 3 | 3 | 100.00 |
| V1 | csr_rw | spi_device_csr_rw | 1.730s | 10.138s | 362.674us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_device_csr_bit_bash | 19.430s | 24.257s | 2.705ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_device_csr_aliasing | 11.840s | 17.196s | 1.141ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_device_csr_mem_rw_with_rand_reset | 1.650s | 6.061s | 106.861us | 3 | 3 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_device_csr_rw | 1.730s | 10.138s | 362.674us | 20 | 20 | 100.00 |
| spi_device_csr_aliasing | 11.840s | 17.196s | 1.141ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_device_mem_walk | 0.570s | 9.084s | 12.083us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_device_mem_partial_access | 1.370s | 9.084s | 127.694us | 5 | 5 | 100.00 |
| V1 | TOTAL | 46 | 62 | 74.19 | ||||
| V2 | csb_read | spi_device_csb_read | 0.560s | 5.061s | 44.470us | 1 | 1 | 100.00 |
| V2 | mem_parity | spi_device_mem_parity | 0.730s | 9.079s | 188.052us | 3 | 3 | 100.00 |
| V2 | mem_cfg | spi_device_ram_cfg | 0.570s | 9.079s | 46.421us | 3 | 3 | 100.00 |
| V2 | tpm_read | spi_device_tpm_rw | 0.560s | 6.068s | 14.598us | 0 | 1 | 0.00 |
| V2 | tpm_write | spi_device_tpm_rw | 0.560s | 6.068s | 14.598us | 0 | 1 | 0.00 |
| V2 | tpm_hw_reg | spi_device_tpm_read_hw_reg | 1.890s | 6.067s | 624.240us | 1 | 1 | 100.00 |
| spi_device_tpm_sts_read | 0.630s | 6.068s | 260.130us | 1 | 1 | 100.00 | ||
| V2 | tpm_fully_random_case | spi_device_tpm_all | 1.220s | 10.112s | 369.709us | 0 | 4 | 0.00 |
| V2 | pass_cmd_filtering | spi_device_pass_cmd_filtering | 4.320s | 8.080s | 10.418ms | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | pass_addr_translation | spi_device_pass_addr_payload_swap | 9.140s | 13.123s | 16.108ms | 3 | 3 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | pass_payload_translation | spi_device_pass_addr_payload_swap | 9.140s | 13.123s | 16.108ms | 3 | 3 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | cmd_info_slots | spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 |
| V2 | cmd_read_status | spi_device_intercept | 1.680s | 6.057s | 283.882us | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | cmd_read_jedec | spi_device_intercept | 1.680s | 6.057s | 283.882us | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | cmd_read_sfdp | spi_device_intercept | 1.680s | 6.057s | 283.882us | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | cmd_fast_read | spi_device_intercept | 1.680s | 6.057s | 283.882us | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | cmd_read_pipeline | spi_device_intercept | 1.680s | 6.057s | 283.882us | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | flash_cmd_upload | spi_device_upload | 2.470s | 7.060s | 1.858ms | 1 | 1 | 100.00 |
| V2 | mailbox_command | spi_device_mailbox | 13.520s | 18.183s | 8.199ms | 1 | 1 | 100.00 |
| V2 | mailbox_cross_outside_command | spi_device_mailbox | 13.520s | 18.183s | 8.199ms | 1 | 1 | 100.00 |
| V2 | mailbox_cross_inside_command | spi_device_mailbox | 13.520s | 18.183s | 8.199ms | 1 | 1 | 100.00 |
| V2 | cmd_read_buffer | spi_device_flash_mode | 27.250s | 33.347s | 10.510ms | 1 | 8 | 12.50 |
| spi_device_read_buffer_direct | 1.930s | 6.055s | 375.998us | 1 | 1 | 100.00 | ||
| V2 | cmd_dummy_cycle | spi_device_mailbox | 13.520s | 18.183s | 8.199ms | 1 | 1 | 100.00 |
| spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 | ||
| V2 | quad_spi | spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 |
| V2 | dual_spi | spi_device_flash_all | 53.930s | 59.659s | 77.708ms | 0 | 8 | 0.00 |
| V2 | 4b_3b_feature | spi_device_cfg_cmd | 2.890s | 9.093s | 1.331ms | 0 | 3 | 0.00 |
| V2 | write_enable_disable | spi_device_cfg_cmd | 2.890s | 9.093s | 1.331ms | 0 | 3 | 0.00 |
| V2 | TPM_with_flash_or_passthrough_mode | spi_device_flash_and_tpm | 5.490s | 10.110s | 4.166ms | 0 | 16 | 0.00 |
| V2 | tpm_and_flash_trans_with_min_inactive_time | spi_device_flash_and_tpm_min_idle | 5.310s | 10.093s | 3.064ms | 0 | 9 | 0.00 |
| V2 | stress_all | spi_device_stress_all | 2.710s | 10.095s | 308.465us | 1 | 9 | 11.11 |
| V2 | alert_test | spi_device_alert_test | 0.570s | 9.079s | 21.649us | 3 | 3 | 100.00 |
| V2 | intr_test | spi_device_intr_test | 0.620s | 7.083s | 15.388us | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_device_tl_errors | 2.930s | 12.128s | 231.564us | 6 | 6 | 100.00 |
| V2 | tl_d_illegal_access | spi_device_tl_errors | 2.930s | 12.128s | 231.564us | 6 | 6 | 100.00 |
| V2 | tl_d_outstanding_access | spi_device_csr_hw_reset | 0.940s | 10.094s | 51.475us | 3 | 3 | 100.00 |
| spi_device_csr_rw | 1.730s | 10.138s | 362.674us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 11.840s | 17.196s | 1.141ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 2.490s | 11.104s | 210.825us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | spi_device_csr_hw_reset | 0.940s | 10.094s | 51.475us | 3 | 3 | 100.00 |
| spi_device_csr_rw | 1.730s | 10.138s | 362.674us | 20 | 20 | 100.00 | ||
| spi_device_csr_aliasing | 11.840s | 17.196s | 1.141ms | 5 | 5 | 100.00 | ||
| spi_device_same_csr_outstanding | 2.490s | 11.104s | 210.825us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 34 | 74 | 45.95 | ||||
| V2S | tl_intg_err | spi_device_sec_cm | 0.940s | 6.056s | 961.875us | 3 | 3 | 100.00 |
| spi_device_tl_intg_err | 11.080s | 15.161s | 915.108us | 6 | 6 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_device_tl_intg_err | 11.080s | 15.161s | 915.108us | 6 | 6 | 100.00 |
| V2S | TOTAL | 9 | 9 | 100.00 | ||||
| V3 | stress_all_with_rand_reset | spi_device_stress_all_with_rand_reset | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | ||||
| Unmapped tests | spi_device_flash_mode_ignore_cmds | 42.800s | 50.557s | 25.804ms | 0 | 9 | 0.00 | |
| TOTAL | 89 | 154 | 57.79 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 22 | 22 | 15 | 68.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 75.22 | 95.85 | 92.13 | 87.22 | 48.94 | 95.14 | 87.98 | 19.30 |
| Target | Elapsed |
|---|---|
| build | 00:07:13 |
| run | 30:46:43 |
| cov_merge | 30:47:37 |
| cov_report | 30:47:52 |
| Total | 30:47:52 |
UVM_ERROR (spi_device_scoreboard.sv:2132) [scoreboard] Check failed (spi_mem.addr_exists(csr_addr)) has 24 failures:
0.spi_device_tpm_all.4970950798137552207029000024516913207339235848180053954356547523845754167524
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest/run.log
UVM_ERROR @ 58532545 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 58542962 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 171265319 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 171275736 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 368677886 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
1.spi_device_tpm_all.32713724242506934883860378921118169455819944516109760293264050191879914913334
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest/run.log
UVM_ERROR @ 11886692 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 11926692 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_FATAL @ 43886692 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 43886692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.spi_device_flash_and_tpm.61833582110827952228112413298771370295091946107038843311136189259580496512513
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 119065686 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 119124510 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 120065694 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 120124518 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 120948054 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
1.spi_device_flash_and_tpm.107167742362373444094933004138105670768597830353736051384793772879565905381379
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 5484549 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 5558231 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 20957769 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 20989347 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_FATAL @ 21505121 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
... and 8 more failures.
0.spi_device_flash_and_tpm_min_idle.53148332481251097978896111292359943517410607220596591383233312837773982426405
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 29790695 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 29803195 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_FATAL @ 30590695 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 30590695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_device_flash_and_tpm_min_idle.2112105744270138302954874571412917981945794769005738427188665525792691283614
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 4562334 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 4572334 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 13012334 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 13022334 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 13162334 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
... and 3 more failures.
1.spi_device_stress_all.43527492261614223528906043406920136455435704941972537669361870676118686813345
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest/run.log
UVM_ERROR @ 311681137 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 311764470 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_FATAL @ 314597792 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 314597792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.spi_device_stress_all.65714736907097664096444278900448258892416479201249562210785790766611120004732
Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest/run.log
UVM_ERROR @ 119135270 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 119156103 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 119385266 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 119406099 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
UVM_ERROR @ 119843592 ps: (spi_device_scoreboard.sv:2132) [uvm_test_top.env.scoreboard] Check failed (spi_mem.addr_exists(csr_addr))
... and 4 more failures.
UVM_ERROR (spi_device_scoreboard.sv:2210) [scoreboard] Check failed item.d_data[TL_DW-*] == tl_ul_side_addr_mode_pending (* [*] vs * [*]) Comparison mismatch [pending], act (*) != exp * has 16 failures:
0.spi_device_cfg_cmd.75791731245128446837767512461685061251330362237637646624245664237008257128987
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 98952185 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 100182185 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_INFO @ 100182185 ps: (spi_device_pass_cmd_filtering_vseq.sv:18) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_cfg_cmd_vseq] running iteration 1, test op = 0x6
UVM_ERROR @ 128102185 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 156032185 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
1.spi_device_cfg_cmd.101551106341810171734351711894317055832874996630306894086601460764471614481842
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest/run.log
UVM_ERROR @ 47802930 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 49657067 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 63802674 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xbff65e) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3f2d78, wel:'h0, busy:'h0}, '{other_status:'h2ffd97, wel:'h0, busy:'h0}}
UVM_INFO @ 68802674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.spi_device_flash_mode_ignore_cmds.70388856765100115873894080802973614143831500880650973422932075494321378623923
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest/run.log
UVM_ERROR @ 4636481080 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 11693214004 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d8a9d) != exp '{'{other_status:'h2362a7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1cfb3b, wel:'h0, busy:'h0}, '{other_status:'h2362a7, wel:'h0, busy:'h0}}
UVM_ERROR @ 11693566948 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d8a9d) != exp '{'{other_status:'h2362a7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1cfb3b, wel:'h0, busy:'h0}, '{other_status:'h2362a7, wel:'h0, busy:'h0}}
UVM_ERROR @ 11702743492 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d8a9d) != exp '{'{other_status:'h2362a7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1cfb3b, wel:'h0, busy:'h0}, '{other_status:'h2362a7, wel:'h0, busy:'h0}}
UVM_ERROR @ 11702890552 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x8d8a9d) != exp '{'{other_status:'h2362a7, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1cfb3b, wel:'h0, busy:'h0}, '{other_status:'h2362a7, wel:'h0, busy:'h0}}
2.spi_device_flash_mode_ignore_cmds.101390072931850832488303874921686361465179704599258189323425663669642568887488
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest/run.log
UVM_ERROR @ 184697731 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 329606677 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 434242936 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5d4871) != exp '{'{other_status:'h17521c, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h175f5c, wel:'h0, busy:'h0}, '{other_status:'h17521c, wel:'h0, busy:'h0}}
UVM_ERROR @ 435242935 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5d4871) != exp '{'{other_status:'h17521c, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h175f5c, wel:'h0, busy:'h0}, '{other_status:'h17521c, wel:'h0, busy:'h0}}
UVM_ERROR @ 436788388 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x5d4871) != exp '{'{other_status:'h17521c, wel:'h0, busy:'h0}, '{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h175f5c, wel:'h0, busy:'h0}, '{other_status:'h17521c, wel:'h0, busy:'h0}}
... and 3 more failures.
0.spi_device_flash_all.49858583409188564818816361175589232325461447978969318850969902962771745969518
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest/run.log
UVM_ERROR @ 348294031 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 2577354031 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf4e0f6) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3d383d, wel:'h0, busy:'h0}}
UVM_ERROR @ 2912054031 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf4e0f6) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3d383d, wel:'h0, busy:'h0}}
UVM_ERROR @ 2912274031 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 2997584031 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0xf4e0f6) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h3d383d, wel:'h0, busy:'h0}}
1.spi_device_flash_all.102019190823926111643575939081872051419956413403423136241923274397743027280049
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest/run.log
UVM_ERROR @ 261848584 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 266848564 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 343098259 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 894762719 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 926679258 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
... and 4 more failures.
1.spi_device_flash_and_tpm_min_idle.43248814926521758244641106694376313154959663836116778215049786784063380335475
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 81636705 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 2130278094 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 2132403111 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 2641198848 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_INFO @ 2913880936 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 0/6
4.spi_device_flash_and_tpm_min_idle.23190373760396989494467084421729842564459398140826025296864265797926844735946
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_ERROR @ 41295365 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 41501545 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 41738652 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 63531878 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 78717035 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
UVM_FATAL (spi_device_scoreboard.sv:2474) [scoreboard] Check failed tpm_read_sw_q.size == * (* [*] vs * [*]) has 10 failures:
Test spi_device_stress_all has 2 failures.
0.spi_device_stress_all.65064970109231454746283638673025539177118840729946795458430530402802781369772
Line 94, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest/run.log
UVM_FATAL @ 3666206904 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 3666206904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.spi_device_stress_all.103342290109507139464193772844036760159486020205232162245495819389220900007784
Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest/run.log
UVM_FATAL @ 109118580 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 109118580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_tpm_all has 1 failures.
2.spi_device_tpm_all.21357223775335501758232636159402736992792379727859628415341623182980302745749
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest/run.log
UVM_FATAL @ 29207136 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 29207136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test spi_device_flash_and_tpm has 5 failures.
3.spi_device_flash_and_tpm.108609260889987697405404086740134634111501479042644313823994311948437961003699
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 168903964 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 168903964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.spi_device_flash_and_tpm.31091095942401227222159873293974365337118688897033972547329505011780847457283
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest/run.log
UVM_FATAL @ 44838377 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44838377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Test spi_device_flash_and_tpm_min_idle has 2 failures.
3.spi_device_flash_and_tpm_min_idle.8753869260662598924238102274455129076335924772282646341239772391377655163650
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 144474099 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 144474099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_device_flash_and_tpm_min_idle.25482761098894696598095472456037299807363482404444467355102852861008259763756
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest/run.log
UVM_FATAL @ 391477025 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 391477025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) CSR last_read_addr compare mismatch act * != exp *` has 3 failures:
0.spi_device_flash_mode.105866582567173017226349161102048443940667525210029139475286433067178671997324
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 394380369 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1 [0x1] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x1 != exp 0x0
UVM_ERROR @ 563631723 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 570715113 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 734008086 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 741299811 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
4.spi_device_flash_mode.114261502039537237450219591580755558360352452806669538746903338667289615435695
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 429689299 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (603 [0x25b] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x25b != exp 0x0
UVM_ERROR @ 721427801 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 902402342 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 983707027 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1185 [0x4a1] vs 603 [0x25b]) CSR last_read_addr compare mismatch act 0x4a1 != exp 0x25b
UVM_INFO @ 1335436872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 3 failures:
1.spi_device_flash_mode_ignore_cmds.26610388966707572622030711439732699453954548126723377153764871867835372769986
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest/run.log
UVM_ERROR @ 290091810 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 290222244 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2374209740 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 2375253212 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x2) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1b37f, wel:'h0, busy:'h0}}
UVM_ERROR @ 2376383640 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x6cdfe) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1b37f, wel:'h0, busy:'h0}}
4.spi_device_flash_mode_ignore_cmds.91362438093796819866023468005815855591238677533181015276363004426718248913966
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest/run.log
UVM_ERROR @ 22830883 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}}
UVM_ERROR @ 23055371 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bfd80, wel:'h0, busy:'h0}}
UVM_ERROR @ 23106391 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare CmdFifoNotEmpty mismatch, act (0x1) != exp 0
UVM_ERROR @ 23208431 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x1) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h1bfd80, wel:'h0, busy:'h0}}
UVM_ERROR @ 23239043 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (33153 [0x8181] vs 0 [0x0]) CSR upload_status compare mismatch act 0x8181 != exp 0x0
... and 1 more failures.
UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufFlip mismatch, act (*) != exp * has 2 failures:
1.spi_device_flash_mode.26817220000819394643831481188427773488022069974004395918797188342317254953099
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 169351736 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 292553633 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1893 [0x765] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x765 != exp 0x0
UVM_ERROR @ 317442497 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 407543417 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2683 [0xa7b] vs 1893 [0x765]) CSR last_read_addr compare mismatch act 0xa7b != exp 0x765
UVM_ERROR @ 446957519 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2939 [0xb7b] vs 2683 [0xa7b]) CSR last_read_addr compare mismatch act 0xb7b != exp 0xa7b
3.spi_device_flash_mode.60040850397333623833476422850735713319694930471893713890698354477875361173373
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 356720828 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 450720734 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (1861 [0x745] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x745 != exp 0x0
UVM_ERROR @ 880942526 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 996609077 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2566 [0xa06] vs 1861 [0x745]) CSR last_read_addr compare mismatch act 0xa06 != exp 0x745
UVM_INFO @ 1174831126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare ReadbufWatermark mismatch, act (*) != exp * has 2 failures:
2.spi_device_flash_mode.50008345086464340845783804212701435502519244842438141633732665370376811331470
Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 4665783741 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 4728216111 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 5772593445 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 5835377166 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufFlip mismatch, act (0x1) != exp 0
UVM_ERROR @ 6039106692 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2235 [0x8bb] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0x8bb != exp 0x0
6.spi_device_flash_mode.93377411736673214643652776919004765824259958361017366702588639197857509316279
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest/run.log
UVM_ERROR @ 260788071 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare ReadbufWatermark mismatch, act (0x1) != exp 0
UVM_ERROR @ 281934581 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (255 [0xff] vs 0 [0x0]) CSR last_read_addr compare mismatch act 0xff != exp 0x0
UVM_INFO @ 554620294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare TpmHeaderNotEmpty mismatch, act (*) != exp * has 1 failures:
0.spi_device_tpm_rw.90574555372152046315315094160009318828983488698931377667302945218498510266769
Line 78, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest/run.log
UVM_ERROR @ 6347869 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare TpmHeaderNotEmpty mismatch, act (0x1) != exp 0
UVM_ERROR @ 14264599 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare TpmHeaderNotEmpty mismatch, act (0x1) != exp 0
UVM_FATAL @ 14597935 ps: (spi_device_scoreboard.sv:2474) [uvm_test_top.env.scoreboard] Check failed tpm_read_sw_q.size == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 14597935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (spi_device_scoreboard.sv:2247) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}, '{other_status:*, wel:*, busy:*}} has 1 failures:
3.spi_device_flash_mode_ignore_cmds.35125494806010712946072997029486309745150803749937000836023908203753252098189
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest/run.log
UVM_ERROR @ 83172540 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x932406) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h24c901, wel:'h0, busy:'h0}}
UVM_ERROR @ 83292540 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x932406) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h24c901, wel:'h0, busy:'h0}}
UVM_ERROR @ 83452540 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x932406) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h24c901, wel:'h0, busy:'h0}}
UVM_ERROR @ 251052540 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x932406) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h24c901, wel:'h0, busy:'h0}}
UVM_ERROR @ 251412540 ps: (spi_device_scoreboard.sv:2247) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x932406) != exp '{'{other_status:'h0, wel:'h0, busy:'h0}, '{other_status:'h24c901, wel:'h0, busy:'h0}}
UVM_ERROR (spi_device_scoreboard.sv:2206) [scoreboard] Check failed item.d_data[*] == exp_addr_mode (* [*] vs * [*]) Comparison mismatch [addr_4b_en], act (*) != exp * has 1 failures:
3.spi_device_flash_all.84749208742202382880319970374249984733649285530221410149317383682865650919116
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest/run.log
UVM_ERROR @ 80365732 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (0 [0x0] vs 1 [0x1]) Comparison mismatch [addr_4b_en], act (0x0) != exp 1
UVM_ERROR @ 80365732 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
UVM_ERROR @ 80365732 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: spi_device_reg_block.addr_mode.addr_4b_en reset value: 0x0
UVM_ERROR @ 99865888 ps: (spi_device_scoreboard.sv:2206) [uvm_test_top.env.scoreboard] Check failed item.d_data[0] == exp_addr_mode (0 [0x0] vs 1 [0x1]) Comparison mismatch [addr_4b_en], act (0x0) != exp 1
UVM_ERROR @ 99865888 ps: (spi_device_scoreboard.sv:2210) [uvm_test_top.env.scoreboard] Check failed item.d_data[TL_DW-1] == tl_ul_side_addr_mode_pending (0 [0x0] vs 1 [0x1]) Comparison mismatch [pending], act (0x0) != exp 1
Offending '(!$isunknown(rdata_o))' has 1 failures:
5.spi_device_flash_all.54986917159887285276614596896783344834706232137072252155461479268789542522175
Line 85, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest/run.log
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 217957459 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
"src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 224: tb.dut.u_readcmd.u_readsram.u_sram_fifo.DataKnown_A: started at 217960063ps failed at 217960063ps
Offending '(!$isunknown(rdata_o))'
UVM_ERROR @ 217960063 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_ERROR (spi_device_scoreboard.sv:2350) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare PayloadNotEmpty mismatch, act (*) != exp * has 1 failures:
14.spi_device_flash_and_tpm.34644232546401523041063936555962114374984499327541629459159122663373963793901
Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest/run.log
UVM_ERROR @ 453701950 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare PayloadNotEmpty mismatch, act (0x1) != exp 0
UVM_ERROR @ 453701950 ps: (spi_device_scoreboard.sv:2350) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (1 [0x1] vs 0 [0x0]) Compare CmdFifoNotEmpty mismatch, act (0x1) != exp 0
UVM_ERROR @ 454416235 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (33153 [0x8181] vs 0 [0x0]) CSR upload_status compare mismatch act 0x8181 != exp 0x0
UVM_ERROR @ 454987663 ps: (spi_device_scoreboard.sv:2512) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (4 [0x4] vs 0 [0x0]) CSR upload_status2 compare mismatch act 0x4 != exp 0x0
UVM_ERROR @ 459273373 ps: (spi_device_scoreboard.sv:2438) [uvm_test_top.env.scoreboard] Check failed upload_cmd_q.size > 0 (0 [0x0] vs 0 [0x0])