SPI_HOST Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke spi_host_smoke 27.660s 1.305m 718.228us 0 10 0.00
V1 csr_hw_reset spi_host_csr_hw_reset 0.660s 9.075s 24.539us 5 5 100.00
V1 csr_rw spi_host_csr_rw 0.550s 7.067s 22.843us 20 20 100.00
V1 csr_bit_bash spi_host_csr_bit_bash 1.460s 9.071s 782.641us 5 5 100.00
V1 csr_aliasing spi_host_csr_aliasing 0.780s 9.072s 124.841us 5 5 100.00
V1 csr_mem_rw_with_rand_reset spi_host_csr_mem_rw_with_rand_reset 0.840s 7.053s 76.009us 4 4 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_host_csr_rw 0.550s 7.067s 22.843us 20 20 100.00
spi_host_csr_aliasing 0.780s 9.072s 124.841us 5 5 100.00
V1 mem_walk spi_host_mem_walk 0.520s 7.060s 26.642us 5 5 100.00
V1 mem_partial_access spi_host_mem_partial_access 0.650s 7.067s 55.551us 5 5 100.00
V1 TOTAL 49 59 83.05
V2 performance spi_host_performance 1.390s 1.020m 37.932us 0 5 0.00
V2 error_event_intr spi_host_overflow_underflow 17.690s 56.219s 406.427us 5 5 100.00
spi_host_error_cmd 0.830s 52.164s 46.706us 3 3 100.00
spi_host_event 6.850s 1.036m 5.286ms 1 1 100.00
V2 clock_rate spi_host_speed 4.750s 1.304m 99.755us 0 9 0.00
V2 speed spi_host_speed 4.750s 1.304m 99.755us 0 9 0.00
V2 chip_select_timing spi_host_speed 4.750s 1.304m 99.755us 0 9 0.00
V2 sw_reset spi_host_sw_reset 5.000s 1.021m 82.338us 0 10 0.00
V2 passthrough_mode spi_host_passthrough_mode 0.810s 35.133s 27.636us 3 3 100.00
V2 cpol_cpha spi_host_speed 4.750s 1.304m 99.755us 0 9 0.00
V2 full_cycle spi_host_speed 4.750s 1.304m 99.755us 0 9 0.00
V2 duplex spi_host_smoke 27.660s 1.305m 718.228us 0 10 0.00
V2 tx_rx_only spi_host_smoke 27.660s 1.305m 718.228us 0 10 0.00
V2 stress_all spi_host_stress_all 13.060s 53.177s 488.076us 0 20 0.00
V2 spien spi_host_spien 5.120s 35.166s 138.430us 0 5 0.00
V2 stall spi_host_status_stall 3.143m 3.632m 26.837ms 0 18 0.00
V2 Idlecsbactive spi_host_idlecsbactive 1.350s 35.136s 82.495us 0 1 0.00
V2 data_fifo_status spi_host_overflow_underflow 17.690s 56.219s 406.427us 5 5 100.00
V2 alert_test spi_host_alert_test 0.780s 35.124s 16.585us 3 3 100.00
V2 intr_test spi_host_intr_test 0.520s 7.059s 81.555us 5 5 100.00
V2 tl_d_oob_addr_access spi_host_tl_errors 1.360s 7.053s 117.404us 5 5 100.00
V2 tl_d_illegal_access spi_host_tl_errors 1.360s 7.053s 117.404us 5 5 100.00
V2 tl_d_outstanding_access spi_host_csr_hw_reset 0.660s 9.075s 24.539us 5 5 100.00
spi_host_csr_rw 0.550s 7.067s 22.843us 20 20 100.00
spi_host_csr_aliasing 0.780s 9.072s 124.841us 5 5 100.00
spi_host_same_csr_outstanding 0.590s 8.059s 117.618us 3 3 100.00
V2 tl_d_partial_access spi_host_csr_hw_reset 0.660s 9.075s 24.539us 5 5 100.00
spi_host_csr_rw 0.550s 7.067s 22.843us 20 20 100.00
spi_host_csr_aliasing 0.780s 9.072s 124.841us 5 5 100.00
spi_host_same_csr_outstanding 0.590s 8.059s 117.618us 3 3 100.00
V2 TOTAL 28 96 29.17
V2S tl_intg_err spi_host_tl_intg_err 1.070s 8.071s 100.473us 8 8 100.00
spi_host_sec_cm 1.130s 36.094s 100.870us 3 3 100.00
V2S sec_cm_bus_integrity spi_host_tl_intg_err 1.070s 8.071s 100.473us 8 8 100.00
V2S TOTAL 11 11 100.00
V3 winbond winbond 0 0 --
V3 stress_all_with_rand_reset spi_host_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
Unmapped tests spi_host_upper_range_clkdiv 53.506m 54.082m 100.003ms 0 7 0.00
TOTAL 88 173 50.87

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 8 8 7 87.50
V2 15 15 8 53.33
V2S 2 2 2 100.00
V3 2 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
75.06 95.39 84.38 74.07 58.82 86.63 93.75 32.35

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52

Failure Buckets