SRAM_CTRL/EXEC_64KB Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 7.870s 44.304s 740.240us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.820s 42.102s 73.750us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.700s 42.091s 22.527us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.560s 40.096s 155.547us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.610s 38.098s 63.866us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.870s 38.102s 858.637us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.700s 42.091s 22.527us 20 20 100.00
sram_ctrl_csr_aliasing 0.610s 38.098s 63.866us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 48.570s 2.253m 1.327ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 51.590s 2.304m 1.286ms 1 1 100.00
V1 TOTAL 58 58 100.00
V2 multiple_keys sram_ctrl_multiple_keys 7.861m 8.431m 6.297ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 1.564m 2.356m 14.115ms 1 1 100.00
V2 bijection sram_ctrl_bijection 7.031m 7.763m 69.131ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 4.601m 6.059m 4.827ms 3 3 100.00
V2 lc_escalation sram_ctrl_lc_escalation 18.160s 1.470m 22.986ms 1 1 100.00
V2 executable sram_ctrl_executable 5.190m 6.542m 5.318ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 2.130s 53.260s 4.300ms 1 1 100.00
sram_ctrl_partial_access_b2b 3.261m 5.643m 89.998ms 4 4 100.00
V2 max_throughput sram_ctrl_max_throughput 45.150s 1.755m 456.213us 1 1 100.00
sram_ctrl_throughput_w_partial_write 4.360s 59.236s 1.241ms 1 1 100.00
sram_ctrl_throughput_w_readback 48.870s 1.821m 2.415ms 1 1 100.00
V2 regwen sram_ctrl_regwen 8.315m 10.187m 12.705ms 3 3 100.00
V2 ram_cfg sram_ctrl_ram_cfg 1.670s 2.786m 203.076us 3 3 100.00
V2 stress_all sram_ctrl_stress_all 38.782m 40.273m 97.020ms 5 5 100.00
V2 alert_test sram_ctrl_alert_test 0.830s 3.103m 39.419us 3 3 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 2.820s 56.094s 496.767us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 2.820s 56.094s 496.767us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.820s 42.102s 73.750us 5 5 100.00
sram_ctrl_csr_rw 0.700s 42.091s 22.527us 20 20 100.00
sram_ctrl_csr_aliasing 0.610s 38.098s 63.866us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.650s 38.101s 29.283us 20 20 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.820s 42.102s 73.750us 5 5 100.00
sram_ctrl_csr_rw 0.700s 42.091s 22.527us 20 20 100.00
sram_ctrl_csr_aliasing 0.610s 38.098s 63.866us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.650s 38.101s 29.283us 20 20 100.00
V2 TOTAL 70 70 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 15.170s 1.052m 15.051ms 3 3 100.00
V2S tl_intg_err sram_ctrl_sec_cm 4.710s 3.203m 796.631us 3 3 100.00
sram_ctrl_tl_intg_err 1.980s 57.110s 1.826ms 7 7 100.00
V2S prim_count_check sram_ctrl_sec_cm 4.710s 3.203m 796.631us 3 3 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 1.980s 57.110s 1.826ms 7 7 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 8.315m 10.187m 12.705ms 3 3 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 8.315m 10.187m 12.705ms 3 3 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.700s 42.091s 22.527us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 5.190m 6.542m 5.318ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 5.190m 6.542m 5.318ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 5.190m 6.542m 5.318ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 18.160s 1.470m 22.986ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 3.310s 3.236m 364.179us 4 4 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 15.170s 1.052m 15.051ms 3 3 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 3.400s 3.070m 1.678ms 4 4 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 7.870s 44.304s 740.240us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 7.870s 44.304s 740.240us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 5.190m 6.542m 5.318ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 4.710s 3.203m 796.631us 3 3 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 18.160s 1.470m 22.986ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 4.710s 3.203m 796.631us 3 3 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 4.710s 3.203m 796.631us 3 3 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 7.870s 44.304s 740.240us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 4.710s 3.203m 796.631us 3 3 100.00
V2S TOTAL 21 21 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 1.747m 3.621m 3.396ms 5 5 100.00
V3 TOTAL 5 5 100.00
TOTAL 154 154 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 17 17 17 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.35 98.75 96.34 85.96 80.00 97.32 96.38 98.70

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52