SRAM_CTRL/MAIN Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 6.410s 10.202s 1.538ms 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 0.890s 11.093s 11.561us 5 5 100.00
V1 csr_rw sram_ctrl_csr_rw 0.910s 12.071s 34.022us 20 20 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.730s 11.088s 175.514us 5 5 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 0.870s 11.063s 24.636us 5 5 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 2.840s 12.101s 372.361us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 0.910s 12.071s 34.022us 20 20 100.00
sram_ctrl_csr_aliasing 0.870s 11.063s 24.636us 5 5 100.00
V1 mem_walk sram_ctrl_mem_walk 1.901m 2.008m 14.397ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 1.754m 1.841m 8.773ms 1 1 100.00
V1 TOTAL 58 58 100.00
V2 multiple_keys sram_ctrl_multiple_keys 6.303m 6.413m 54.132ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 2.540m 2.627m 3.963ms 1 1 100.00
V2 bijection sram_ctrl_bijection 21.999m 22.119m 402.823ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 12.975m 13.544m 15.986ms 3 3 100.00
V2 lc_escalation sram_ctrl_lc_escalation 32.450s 36.394s 10.409ms 1 1 100.00
V2 executable sram_ctrl_executable 8.925m 8.999m 31.699ms 3 3 100.00
V2 partial_access sram_ctrl_partial_access 3.360s 7.159s 6.583ms 1 1 100.00
sram_ctrl_partial_access_b2b 4.766m 6.126m 177.591ms 4 4 100.00
V2 max_throughput sram_ctrl_max_throughput 51.230s 55.488s 9.335ms 1 1 100.00
sram_ctrl_throughput_w_partial_write 10.730s 15.199s 1.502ms 1 1 100.00
sram_ctrl_throughput_w_readback 7.700s 12.159s 3.149ms 1 1 100.00
V2 regwen sram_ctrl_regwen 10.695m 10.808m 70.352ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 3.090s 44.245s 653.711us 3 3 100.00
V2 stress_all sram_ctrl_stress_all 59.324m 59.399m 360.855ms 5 5 100.00
V2 alert_test sram_ctrl_alert_test 0.850s 1.302m 15.476us 3 3 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 3.150s 13.104s 560.512us 20 20 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 3.150s 13.104s 560.512us 20 20 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 0.890s 11.093s 11.561us 5 5 100.00
sram_ctrl_csr_rw 0.910s 12.071s 34.022us 20 20 100.00
sram_ctrl_csr_aliasing 0.870s 11.063s 24.636us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 12.072s 39.111us 3 3 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 0.890s 11.093s 11.561us 5 5 100.00
sram_ctrl_csr_rw 0.910s 12.071s 34.022us 20 20 100.00
sram_ctrl_csr_aliasing 0.870s 11.063s 24.636us 5 5 100.00
sram_ctrl_same_csr_outstanding 0.870s 12.072s 39.111us 3 3 100.00
V2 TOTAL 53 53 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 19.520s 28.186s 13.250ms 4 4 100.00
V2S tl_intg_err sram_ctrl_sec_cm 4.310s 1.469m 1.286ms 4 4 100.00
sram_ctrl_tl_intg_err 2.420s 12.067s 495.798us 7 7 100.00
V2S prim_count_check sram_ctrl_sec_cm 4.310s 1.469m 1.286ms 4 4 100.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.420s 12.067s 495.798us 7 7 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 10.695m 10.808m 70.352ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 10.695m 10.808m 70.352ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 0.910s 12.071s 34.022us 20 20 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 8.925m 8.999m 31.699ms 3 3 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 8.925m 8.999m 31.699ms 3 3 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 8.925m 8.999m 31.699ms 3 3 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 32.450s 36.394s 10.409ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 6.490s 42.093s 3.046ms 3 3 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 19.520s 28.186s 13.250ms 4 4 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 6.140s 43.244s 2.635ms 3 3 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 6.410s 10.202s 1.538ms 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 6.410s 10.202s 1.538ms 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 8.925m 8.999m 31.699ms 3 3 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 4.310s 1.469m 1.286ms 4 4 100.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 32.450s 36.394s 10.409ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 4.310s 1.469m 1.286ms 4 4 100.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 4.310s 1.469m 1.286ms 4 4 100.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 6.410s 10.202s 1.538ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 4.310s 1.469m 1.286ms 4 4 100.00
V2S TOTAL 21 21 100.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 46.220s 1.803m 20.195ms 6 6 100.00
V3 TOTAL 6 6 100.00
TOTAL 138 138 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 17 17 17 100.00
V2S 5 5 5 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.13 98.75 96.34 91.27 80.00 97.32 96.38 98.89

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52