SRAM_CTRL/RET Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.640s	33.164s	7.931ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.800s	2.754m	38.764us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.810s	2.754m	100.996us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.480s	2.754m	88.954us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.770s	2.320m	108.466us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.760s	1.670m	10.004ms	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.810s	2.754m	100.996us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	2.320m	108.466us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.880s	1.068m	96.018us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.390s	1.068m	203.261us	1	1	100.00
V1		TOTAL				55	58	94.83
V2	multiple_keys	sram_ctrl_multiple_keys	10.191m	10.602m	87.510ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.991m	2.405m	2.213ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	39.860s	1.086m	5.507ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	11.017m	12.459m	26.579ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.990s	37.114s	1.374ms	1	1	100.00
V2	executable	sram_ctrl_executable	13.600m	14.453m	13.821ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.070s	28.126s	639.896us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.176m	5.675m	63.935ms	4	4	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.210s	29.120s	193.263us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.860s	39.129s	267.191us	1	1	100.00
		sram_ctrl_throughput_w_readback	52.340s	1.437m	270.630us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.471m	5.392m	8.493ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.750s	1.486m	26.440us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	49.540m	52.197m	61.748ms	6	6	100.00
V2	alert_test	sram_ctrl_alert_test	0.850s	1.970m	34.722us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.270s	2.920m	133.234us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.270s	2.920m	133.234us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.800s	2.754m	38.764us	5	5	100.00
		sram_ctrl_csr_rw	0.810s	2.754m	100.996us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	2.320m	108.466us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	2.236m	134.108us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.800s	2.754m	38.764us	5	5	100.00
		sram_ctrl_csr_rw	0.810s	2.754m	100.996us	20	20	100.00
		sram_ctrl_csr_aliasing	0.770s	2.320m	108.466us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.870s	2.236m	134.108us	20	20	100.00
V2		TOTAL				69	69	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.020s	2.770m	1.822ms	3	3	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.480s	2.803m	1.003ms	4	4	100.00
		sram_ctrl_tl_intg_err	2.210s	2.770m	2.059ms	5	5	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.480s	2.803m	1.003ms	4	4	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.210s	2.770m	2.059ms	5	5	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.471m	5.392m	8.493ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.471m	5.392m	8.493ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.810s	2.754m	100.996us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	13.600m	14.453m	13.821ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	13.600m	14.453m	13.821ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	13.600m	14.453m	13.821ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.990s	37.114s	1.374ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.930s	1.469m	647.740us	3	3	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.020s	2.770m	1.822ms	3	3	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.900s	2.003m	50.101us	4	4	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.640s	33.164s	7.931ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.640s	33.164s	7.931ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	13.600m	14.453m	13.821ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.480s	2.803m	1.003ms	4	4	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.990s	37.114s	1.374ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.480s	2.803m	1.003ms	4	4	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.480s	2.803m	1.003ms	4	4	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.640s	33.164s	7.931ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.480s	2.803m	1.003ms	4	4	100.00
V2S		TOTAL				19	19	100.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.956m	4.339m	2.882ms	5	5	100.00
V3		TOTAL				5	5	100.00
		TOTAL				148	151	98.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	17	17	17	100.00
V2S	5	5	5	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.10	98.70	96.46	91.21	80.00	97.26	96.35	98.70

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 7.sram_ctrl_csr_mem_rw_with_rand_reset.42584516241063340638951177263475276168317633787758167032509946242723632890232
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/7.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  99651857 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (7 [0x7] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
        UVM_INFO @  99651857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (sram_ctrl_base_vseq.sv:168) [sram_ctrl_common_vseq] Timed out waiting for initialization done has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 9.sram_ctrl_csr_mem_rw_with_rand_reset.73058433137273864035843087793629772892141440336614829790873623104118875319394
      Line 105, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/9.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_FATAL @ 10004445073 ps: (sram_ctrl_base_vseq.sv:168) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Timed out waiting for initialization done
        UVM_INFO @ 10004445073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 15.sram_ctrl_csr_mem_rw_with_rand_reset.1846197113876346262178591644856378135599989369056713524260488874992988520254
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 252885193 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (3 [0x3] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @ 252885193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---