SYSRST_CTRL Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	5.860s	1.886m	2.113ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	4.100s	1.852m	2.467ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	7.030s	1.502m	2.403ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.820s	1.202m	2.327ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	9.360s	38.246s	6.027ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	4.520s	36.197s	2.050ms	3	3	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.829m	3.404m	75.975ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	7.990s	38.286s	2.774ms	3	3	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	5.340s	20.218s	2.062ms	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	4.520s	36.197s	2.050ms	3	3	100.00
		sysrst_ctrl_csr_aliasing	7.990s	38.286s	2.774ms	3	3	100.00
V1		TOTAL				32	32	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	4.342m	4.699m	136.582ms	7	7	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	3.480m	3.895m	137.891ms	30	30	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	8.200s	1.152m	3.001ms	4	4	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	10.880s	59.197s	3.669ms	13	13	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.550s	1.235m	2.508ms	3	3	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.390s	58.140s	2.047ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	4.860s	42.146s	2.816ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.330s	49.130s	2.628ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	3.942m	4.786m	1.668s	7	7	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.670m	2.523m	40.008ms	6	6	100.00
V2	stress_all	sysrst_ctrl_stress_all	5.286m	6.373m	203.711ms	21	22	95.45
V2	alert_test	sysrst_ctrl_alert_test	2.090s	1.152m	2.034ms	3	3	100.00
V2	intr_test	sysrst_ctrl_intr_test	5.780s	42.188s	2.013ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.490s	51.210s	2.040ms	5	5	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.490s	51.210s	2.040ms	5	5	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	9.360s	38.246s	6.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	4.520s	36.197s	2.050ms	3	3	100.00
		sysrst_ctrl_csr_aliasing	7.990s	38.286s	2.774ms	3	3	100.00
		sysrst_ctrl_same_csr_outstanding	9.450s	42.369s	5.209ms	3	3	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	9.360s	38.246s	6.027ms	5	5	100.00
		sysrst_ctrl_csr_rw	4.520s	36.197s	2.050ms	3	3	100.00
		sysrst_ctrl_csr_aliasing	7.990s	38.286s	2.774ms	3	3	100.00
		sysrst_ctrl_same_csr_outstanding	9.450s	42.369s	5.209ms	3	3	100.00
V2		TOTAL				155	156	99.36
V2S	tl_intg_err	sysrst_ctrl_sec_cm	28.700s	1.654m	22.030ms	3	3	100.00
		sysrst_ctrl_tl_intg_err	1.157m	1.856m	42.458ms	4	4	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.157m	1.856m	42.458ms	4	4	100.00
V2S		TOTAL				7	7	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	17.270s	1.188m	6.694ms	6	6	100.00
V3		TOTAL				6	6	100.00
		TOTAL				200	201	99.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	14	93.33
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.18	99.52	98.16	100.00	96.79	99.59	98.18	88.05

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:892) [sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred! has 1 failures:
  • Test sysrst_ctrl_stress_all has 1 failures.

    • 16.sysrst_ctrl_stress_all.86936446438579003033121504077945884778528057583605345907893420833713102709718
      Line 660, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest/run.log

        UVM_FATAL @ 17565568208 ps: (cip_base_vseq.sv:892) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!
        UVM_INFO @ 17565568208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---