UART Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.200s	13.066s	905.849us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.710s	11.104s	21.397us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.760s	10.094s	51.778us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.500s	10.095s	132.069us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	9.080s	20.531us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.180s	10.069s	30.029us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.760s	10.094s	51.778us	20	20	100.00
		uart_csr_aliasing	0.750s	9.080s	20.531us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	base_random_seq	uart_tx_rx	2.011m	2.588m	107.560ms	5	5	100.00
V2	parity	uart_smoke	2.200s	13.066s	905.849us	1	1	100.00
		uart_tx_rx	2.011m	2.588m	107.560ms	5	5	100.00
V2	parity_error	uart_intr	1.069m	1.636m	64.549ms	7	7	100.00
		uart_rx_parity_err	1.169m	1.737m	80.041ms	1	1	100.00
V2	watermark	uart_tx_rx	2.011m	2.588m	107.560ms	5	5	100.00
		uart_intr	1.069m	1.636m	64.549ms	7	7	100.00
V2	fifo_full	uart_fifo_full	2.609m	3.173m	98.496ms	7	7	100.00
V2	fifo_overflow	uart_fifo_overflow	1.023m	1.786m	293.471ms	5	5	100.00
V2	fifo_reset	uart_fifo_reset	4.740m	5.594m	251.247ms	58	58	100.00
V2	rx_frame_err	uart_intr	1.069m	1.636m	64.549ms	7	7	100.00
V2	rx_break_err	uart_intr	1.069m	1.636m	64.549ms	7	7	100.00
V2	rx_timeout	uart_intr	1.069m	1.636m	64.549ms	7	7	100.00
V2	perf	uart_perf	3.744m	4.308m	33.727ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.350s	35.082s	348.231us	1	1	100.00
V2	line_loopback	uart_loopback	1.350s	35.082s	348.231us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.490s	36.094s	22.248ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	8.360s	33.084s	35.605ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.820s	37.099s	727.064us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	39.730s	58.159s	7.946ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	12.101m	12.706m	132.643ms	5	5	100.00
V2	stress_all	uart_stress_all	6.561m	7.251m	176.480ms	11	12	91.67
V2	alert_test	uart_alert_test	0.780s	1.018m	11.915us	3	3	100.00
V2	intr_test	uart_intr_test	0.670s	7.060s	22.912us	3	3	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.580s	11.091s	149.012us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.580s	11.091s	149.012us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.710s	11.104s	21.397us	5	5	100.00
		uart_csr_rw	0.760s	10.094s	51.778us	20	20	100.00
		uart_csr_aliasing	0.750s	9.080s	20.531us	5	5	100.00
		uart_same_csr_outstanding	0.720s	9.069s	107.229us	3	3	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.710s	11.104s	21.397us	5	5	100.00
		uart_csr_rw	0.760s	10.094s	51.778us	20	20	100.00
		uart_csr_aliasing	0.750s	9.080s	20.531us	5	5	100.00
		uart_same_csr_outstanding	0.720s	9.069s	107.229us	3	3	100.00
V2		TOTAL				133	135	98.52
V2S	tl_intg_err	uart_sec_cm	1.030s	56.094s	330.034us	3	3	100.00
		uart_tl_intg_err	1.390s	10.085s	145.530us	6	6	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.390s	10.085s	145.530us	6	6	100.00
V2S		TOTAL				9	9	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.767m	2.621m	5.406ms	10	10	100.00
V3		TOTAL				10	10	100.00
		TOTAL				208	210	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	16	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	99.48	98.25	74.67	--	98.14	97.12	99.57

Simulation Wall Clock Time

Target	Elapsed
build	00:07:13
run	30:46:43
cov_merge	30:47:37
cov_report	30:47:52
Total	30:47:52

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.25065608516776895068165987228403312341921414396344176366790165994872930611717
      Line 83, in log /home/runner/_work/pavona/pavona/scratch/main/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 20943514573 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 20943514573 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 21836014407 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 3
        UVM_ERROR @ 21836032589 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 21836050771 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (255 [0xff] vs 225 [0xe1]) reg name: uart_reg_block.rdata
      

  • Test uart_stress_all has 1 failures.

    • 9.uart_stress_all.100502697506809334456209421359276456208174704343567038144922148894218497211178
      Line 91, in log /home/runner/_work/pavona/pavona/scratch/main/uart-sim-vcs/9.uart_stress_all/latest/run.log

        UVM_ERROR @ 85797462537 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 85797462537 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 88148217762 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 88148217762 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 89625185982 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0