USBDEV Simulation Results

Sunday August 02 2026 00:03:30 UTC

GitHub Revision: 0ff052588e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 0.660s 25.256s 207.796us 1 1 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.640s 5.167s 175.772us 3 3 100.00
V1 csr_rw usbdev_csr_rw 0.760s 9.570s 131.223us 20 20 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 5.230s 9.335s 1.508ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 1.830s 8.332s 420.815us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 1.240s 7.591s 91.457us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.760s 9.570s 131.223us 20 20 100.00
usbdev_csr_aliasing 1.830s 8.332s 420.815us 5 5 100.00
V1 mem_walk usbdev_mem_walk 2.370s 8.312s 480.985us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.260s 9.432s 84.170us 5 5 100.00
V1 TOTAL 64 64 100.00
V2 in_trans usbdev_in_trans 0.660s 29.206s 263.250us 1 1 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 0.820s 11.343s 437.195us 1 1 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.570s 34.714s 46.814us 5 5 100.00
V2 av_buffer usbdev_av_buffer 0.570s 10.393s 154.443us 1 1 100.00
V2 rx_fifo usbdev_pkt_buffer 17.270s 44.611s 14.379ms 3 3 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 0.740s 26.142s 357.374us 3 3 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.630s 21.153s 163.055us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 0.680s 21.174s 268.035us 1 1 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 0.680s 34.778s 253.094us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0.650s 21.176s 231.181us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 0.660s 21.218s 219.476us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 0.640s 29.420s 177.961us 3 3 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.620s 29.228s 189.093us 1 1 100.00
usbdev_stream_len_max 0.810s 22.313s 391.175us 1 1 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 0.660s 29.198s 266.915us 1 1 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.590s 25.228s 150.831us 1 1 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.590s 25.224s 159.062us 1 1 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 0.650s 18.168s 188.075us 1 1 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 0.620s 18.165s 192.100us 1 1 100.00
V2 out_stall usbdev_out_stall 0.620s 21.129s 180.676us 1 1 100.00
V2 in_stall usbdev_in_stall 0.580s 29.211s 152.440us 1 1 100.00
V2 out_iso usbdev_out_iso 0.600s 21.146s 186.139us 1 1 100.00
V2 in_iso usbdev_in_iso 0.700s 29.210s 269.077us 1 1 100.00
V2 pkt_received usbdev_pkt_received 0.610s 18.184s 178.940us 1 1 100.00
V2 pkt_sent usbdev_pkt_sent 0.620s 21.190s 182.486us 1 1 100.00
V2 disconnected usbdev_disconnected 0.600s 25.249s 149.015us 3 3 100.00
V2 host_lost usbdev_host_lost 5.170s 34.630s 4.166ms 3 3 100.00
V2 link_reset usbdev_link_reset 0.620s 29.383s 169.263us 3 3 100.00
V2 link_suspend usbdev_link_suspend 7.790s 37.252s 10.838ms 4 4 100.00
V2 link_resume usbdev_link_resume 14.810s 43.303s 27.308ms 3 3 100.00
V2 av_empty usbdev_av_empty 0.610s 25.372s 155.561us 4 4 100.00
V2 rx_full usbdev_rx_full 0.790s 34.863s 371.897us 5 5 100.00
V2 av_overflow usbdev_av_overflow 0.620s 29.507s 192.493us 5 5 100.00
V2 link_in_err usbdev_link_in_err 0.650s 29.207s 244.206us 1 1 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.630s 25.893s 175.912us 3 3 100.00
V2 rx_pid_err usbdev_rx_pid_err 0.660s 29.485s 188.757us 3 3 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.610s 25.288s 151.183us 3 3 100.00
V2 link_out_err usbdev_link_out_err 0.920s 30.211s 546.022us 3 3 100.00
V2 enable usbdev_enable 0.510s 12.223s 47.244us 1 1 100.00
V2 resume_link_active usbdev_resume_link_active 10.690s 40.180s 20.174ms 3 3 100.00
V2 device_address usbdev_device_address 28.190s 1.039m 38.840ms 7 7 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 0.810s 26.181s 413.288us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.600s 25.261s 160.982us 1 1 100.00
V2 endpoint_access usbdev_endpoint_access 1.020s 12.224s 619.540us 1 1 100.00
V2 disable_endpoint usbdev_disable_endpoint 1.330s 30.410s 930.031us 3 3 100.00
V2 endpoint_types usbdev_endpoint_types 1.080s 29.769s 557.068us 66 66 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.610s 21.131s 199.208us 1 1 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.610s 25.259s 198.079us 1 1 100.00
V2 nak_trans usbdev_nak_trans 0.650s 29.413s 194.368us 3 3 100.00
V2 stall_trans usbdev_stall_trans 0.580s 25.331s 168.522us 1 1 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 0.770s 34.775s 328.819us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 0.620s 25.330s 219.861us 1 1 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.600s 21.152s 160.172us 1 1 100.00
V2 streaming_test usbdev_streaming_out 41.840s 1.121m 3.187ms 1 1 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 1.341m 1.787m 117.216ms 5 5 100.00
usbdev_freq_loclk 1.150m 1.634m 94.114ms 3 3 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 1.673m 2.060m 116.248ms 4 4 100.00
usbdev_freq_loclk_max 1.340m 1.637m 120.885ms 3 3 100.00
V2 max_phase_error usbdev_freq_phase 1.491m 1.973m 113.176ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 15.300s 40.380s 3.249ms 1 1 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 32.720s 1.024m 2.467ms 1 1 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 23.180s 33.425s 5.716ms 1 1 100.00
V2 device_timeout usbdev_device_timeout 15.160s 26.365s 4.996ms 1 1 100.00
V2 packet_buffer usbdev_pkt_buffer 17.270s 44.611s 14.379ms 3 3 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 0.790s 26.152s 461.908us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 15.760s 36.513s 29.755ms 3 3 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 12.920s 33.415s 19.150ms 4 4 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 6.200s 26.357s 11.340ms 3 3 100.00
V2 invalid_sync usbdev_invalid_sync 11.820s 37.251s 2.482ms 1 1 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 45.610s 1.172m 3.358ms 1 1 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 57.930s 1.270m 4.361ms 5 5 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 30.020s 52.810s 6.105ms 10 10 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 41.940s 1.183m 3.532ms 3 3 100.00
V2 rand_suspends usbdev_rand_suspends 1.317m 1.637m 9.603ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 29.970s 55.450s 2.279ms 3 3 100.00
usbdev_max_usb_traffic 41.840s 1.064m 3.097ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 51.560s 1.292m 7.282ms 7 7 100.00
V2 in_packet_retraction usbdev_iso_retraction 15.620s 44.288s 4.801ms 1 1 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 1.520s 34.779s 1.217ms 7 7 100.00
V2 setup_priority usbdev_setup_priority 0.910s 30.369s 511.945us 3 3 100.00
V2 fifo_resets usbdev_fifo_rst 1.160s 13.167s 357.968us 1 1 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 0.980s 34.773s 567.130us 8 8 100.00
V2 fifo_levels usbdev_fifo_levels 0.900s 34.649s 294.078us 58 58 100.00
V2 rxenable_out_conditional usbdev_rxenable_out 0.650s 34.858s 140.424us 5 5 100.00
V2 intr_test usbdev_intr_test 0.600s 5.195s 92.955us 7 7 100.00
V2 alert_test usbdev_alert_test 0.520s 25.540s 30.802us 3 3 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 1.970s 9.453s 292.840us 5 5 100.00
V2 tl_d_illegal_access usbdev_tl_errors 1.970s 9.453s 292.840us 5 5 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.640s 5.167s 175.772us 3 3 100.00
usbdev_csr_rw 0.760s 9.570s 131.223us 20 20 100.00
usbdev_csr_aliasing 1.830s 8.332s 420.815us 5 5 100.00
usbdev_same_csr_outstanding 1.030s 9.206s 190.669us 3 3 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.640s 5.167s 175.772us 3 3 100.00
usbdev_csr_rw 0.760s 9.570s 131.223us 20 20 100.00
usbdev_csr_aliasing 1.830s 8.332s 420.815us 5 5 100.00
usbdev_same_csr_outstanding 1.030s 9.206s 190.669us 3 3 100.00
V2 TOTAL 370 370 100.00
V2S tl_intg_err usbdev_sec_cm 1.430s 26.542s 1.732ms 3 3 100.00
usbdev_tl_intg_err 2.760s 10.723s 1.762ms 8 8 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 2.760s 10.723s 1.762ms 8 8 100.00
V2S TOTAL 11 11 100.00
V3 dpi_config_host usbdev_dpi_config_host 23.290s 34.446s 5.109ms 1 1 100.00
V3 TOTAL 1 1 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.550s 34.779s 74.068us 0 10 0.00
usbdev_stress_all 0.490s 21.452s 0 1 0.00
TOTAL 446 457 97.59

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 87 87 87 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.88 98.79 95.53 97.23 93.22 98.34 96.20 98.82

Simulation Wall Clock Time

Target Elapsed
build 00:07:13
run 30:46:43
cov_merge 30:47:37
cov_report 30:47:52
Total 30:47:52

Failure Buckets