AC_RANGE_CHECK/DRAGONFLY Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	ac_range_check_smoke	ac_range_check_smoke	23.530s	27.353s	3.659ms	27	27	100.00
V1	ac_range_check_smoke_racl	ac_range_check_smoke_racl	32.640s	35.928s	2.591ms	31	31	100.00
V1	csr_hw_reset	ac_range_check_csr_hw_reset	1.000s	5.911s	40.882us	5	5	100.00
V1	csr_rw	ac_range_check_csr_rw	1.110s	5.892s	49.955us	20	20	100.00
V1	csr_bit_bash	ac_range_check_csr_bit_bash	23.010s	27.566s	9.782ms	5	5	100.00
V1	csr_aliasing	ac_range_check_csr_aliasing	17.710s	21.899s	5.842ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	ac_range_check_csr_mem_rw_with_rand_reset	1.370s	6.703s	25.388us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	ac_range_check_csr_rw	1.110s	5.892s	49.955us	20	20	100.00
		ac_range_check_csr_aliasing	17.710s	21.899s	5.842ms	5	5	100.00
V1		TOTAL				113	113	100.00
V2	ac_range_check_lock_range	ac_range_check_lock_range	1.360s	5.340s	54.997us	22	22	100.00
V2	ac_range_bypass_enable	ac_range_check_bypass	18.030s	22.011s	2.344ms	1	1	100.00
V2	stress_all	ac_range_check_stress_all	2.758m	2.814m	12.850ms	56	62	90.32
V2	alert_test	ac_range_check_alert_test	0.480s	4.299s	13.457us	3	3	100.00
V2	intr_test	ac_range_check_intr_test	0.480s	5.926s	13.868us	3	3	100.00
V2	tl_d_oob_addr_access	ac_range_check_tl_errors	2.590s	6.967s	334.548us	20	20	100.00
V2	tl_d_illegal_access	ac_range_check_tl_errors	2.590s	6.967s	334.548us	20	20	100.00
V2	tl_d_outstanding_access	ac_range_check_csr_hw_reset	1.000s	5.911s	40.882us	5	5	100.00
		ac_range_check_csr_rw	1.110s	5.892s	49.955us	20	20	100.00
		ac_range_check_csr_aliasing	17.710s	21.899s	5.842ms	5	5	100.00
		ac_range_check_same_csr_outstanding	2.880s	8.338s	197.209us	20	20	100.00
V2	tl_d_partial_access	ac_range_check_csr_hw_reset	1.000s	5.911s	40.882us	5	5	100.00
		ac_range_check_csr_rw	1.110s	5.892s	49.955us	20	20	100.00
		ac_range_check_csr_aliasing	17.710s	21.899s	5.842ms	5	5	100.00
		ac_range_check_same_csr_outstanding	2.880s	8.338s	197.209us	20	20	100.00
V2		TOTAL				125	131	95.42
V2S	shadow_reg_update_error	ac_range_check_shadow_reg_errors	14.990s	19.702s	1.202ms	6	6	100.00
V2S	shadow_reg_read_clear_staged_value	ac_range_check_shadow_reg_errors	14.990s	19.702s	1.202ms	6	6	100.00
V2S	shadow_reg_storage_error	ac_range_check_shadow_reg_errors	14.990s	19.702s	1.202ms	6	6	100.00
V2S	shadowed_reset_glitch	ac_range_check_shadow_reg_errors	14.990s	19.702s	1.202ms	6	6	100.00
V2S	shadow_reg_update_error_with_csr_rw	ac_range_check_shadow_reg_errors_with_csr_rw	1.230m	1.295m	5.170ms	3	3	100.00
V2S	tl_intg_err	ac_range_check_sec_cm	0.470s	4.433s	21.845us	5	5	100.00
		ac_range_check_tl_intg_err	6.280s	10.790s	395.769us	15	15	100.00
V2S		TOTAL				29	29	100.00
V3	stress_all_with_rand_reset	ac_range_check_stress_all_with_rand_reset	4.271m	4.339m	8.794ms	5	5	100.00
V3		TOTAL				5	5	100.00
	Unmapped tests	ac_range_check_smoke_high_threshold	22.400s	25.416s	23.010ms	16	16	100.00
		ac_range_check_rst_safe_smoke	2.923m	2.986m	100.094ms	15	16	93.75
		TOTAL				303	310	97.74

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	1	50.00
V1	7	7	7	100.00
V2	7	7	6	85.71
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.60	99.87	98.38	83.44	--	99.55	97.75	82.59

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state has 6 failures:
  • Test ac_range_check_stress_all has 6 failures.

    • 44.ac_range_check_stress_all.101506689489037086158964912187275799512620762648426915235717048093612923451337
      Line 27548, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/ac_range_check_top_dragonfly-sim-vcs/44.ac_range_check_stress_all/latest/run.log

        UVM_ERROR @ 30754216393 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 30754216393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.ac_range_check_stress_all.98223771621678372294675995451429375438077935226913435827412257685002194781765
      Line 17564, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/ac_range_check_top_dragonfly-sim-vcs/45.ac_range_check_stress_all/latest/run.log

        UVM_ERROR @ 30352447271 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 30352447271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
  • Test ac_range_check_rst_safe_smoke has 1 failures.

    • 13.ac_range_check_rst_safe_smoke.264431455396598169229096076233953345445972592920899711237977058925478318342
      Line 4612, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/ac_range_check_top_dragonfly-sim-vcs/13.ac_range_check_rst_safe_smoke/latest/run.log

            Offending '(pend_req[h2d.a_source].pend == 0)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2694117042ps failed at 2694117042ps
            Offending '(pend_req[h2d.a_source].pend == 0)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2694234690ps failed at 2694234690ps
            Offending '(pend_req[h2d.a_source].pend == 0)'