ACC/PQC Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	acc_smoke	5.120s	15.215s	61.830us	1	1	100.00
V1	single_binary	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V1	csr_hw_reset	acc_csr_hw_reset	1.160s	5.246s	21.110us	3	3	100.00
V1	csr_rw	acc_csr_rw	1.070s	5.605s	66.408us	20	20	100.00
V1	csr_bit_bash	acc_csr_bit_bash	1.710s	5.694s	134.630us	5	5	100.00
V1	csr_aliasing	acc_csr_aliasing	1.110s	5.269s	76.034us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	acc_csr_mem_rw_with_rand_reset	3.090s	6.967s	190.703us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	acc_csr_rw	1.070s	5.605s	66.408us	20	20	100.00
		acc_csr_aliasing	1.110s	5.269s	76.034us	5	5	100.00
V1	mem_walk	acc_mem_walk	2.526m	2.606m	39.130ms	5	5	100.00
V1	mem_partial_access	acc_mem_partial_access	46.670s	50.946s	800.190us	5	5	100.00
V1		TOTAL				125	126	99.21
V2	reset_recovery	acc_reset	23.920s	30.289s	430.367us	7	7	100.00
V2	multi_error	acc_multi_err	19.030s	41.237s	508.638us	4	4	100.00
V2	back_to_back	acc_multi	7.352m	8.094m	6.344ms	11	11	100.00
V2	stress_all	acc_stress_all	54.630s	1.187m	2.035ms	14	15	93.33
V2	lc_escalation	acc_escalate	14.450s	20.889s	638.602us	21	22	95.45
V2	zero_state_err_urnd	acc_zero_state_err_urnd	2.660s	8.592s	30.941us	5	5	100.00
V2	sw_errs_fatal_chk	acc_sw_errs_fatal_chk	10.670s	18.966s	80.703us	11	11	100.00
V2	alert_test	acc_alert_test	1.100s	5.294s	40.788us	3	3	100.00
V2	intr_test	acc_intr_test	1.510s	5.970s	32.328us	50	50	100.00
V2	tl_d_oob_addr_access	acc_tl_errors	3.410s	7.817s	1.548ms	20	20	100.00
V2	tl_d_illegal_access	acc_tl_errors	3.410s	7.817s	1.548ms	20	20	100.00
V2	tl_d_outstanding_access	acc_csr_hw_reset	1.160s	5.246s	21.110us	3	3	100.00
		acc_csr_rw	1.070s	5.605s	66.408us	20	20	100.00
		acc_csr_aliasing	1.110s	5.269s	76.034us	5	5	100.00
		acc_same_csr_outstanding	1.070s	4.586s	18.806us	3	3	100.00
V2	tl_d_partial_access	acc_csr_hw_reset	1.160s	5.246s	21.110us	3	3	100.00
		acc_csr_rw	1.070s	5.605s	66.408us	20	20	100.00
		acc_csr_aliasing	1.110s	5.269s	76.034us	5	5	100.00
		acc_same_csr_outstanding	1.070s	4.586s	18.806us	3	3	100.00
V2		TOTAL				149	151	98.68
V2S	mem_integrity	acc_imem_err	4.040s	9.567s	78.390us	4	4	100.00
		acc_dmem_err	7.940s	15.007s	743.130us	7	7	100.00
V2S	internal_integrity	acc_alu_bignum_mod_err	11.420s	19.060s	89.971us	7	7	100.00
		acc_controller_ispr_rdata_err	24.790s	32.378s	354.707us	5	5	100.00
		acc_mac_bignum_acc_err	19.500s	26.818s	3.245ms	8	8	100.00
		acc_urnd_err	1.760s	8.144s	44.243us	4	4	100.00
V2S	kmac_error	acc_kmac_err	2.970s	18.204s	86.806us	9	10	90.00
V2S	illegal_bus_access	acc_illegal_mem_acc	2.890s	8.239s	102.327us	5	5	100.00
V2S	acc_mem_gnt_acc_err	acc_mem_gnt_acc_err	2.980s	8.485s	63.902us	3	3	100.00
V2S	acc_non_sec_partial_wipe	acc_partial_wipe	3.030s	8.593s	41.278us	6	7	85.71
V2S	tl_intg_err	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
		acc_tl_intg_err	5.650s	9.860s	234.586us	6	6	100.00
V2S	passthru_mem_tl_intg_err	acc_passthru_mem_tl_intg_err	32.060s	37.084s	773.320us	5	5	100.00
V2S	prim_fsm_check	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	prim_count_check	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_mem_scramble	acc_smoke	5.120s	15.215s	61.830us	1	1	100.00
V2S	sec_cm_data_mem_integrity	acc_dmem_err	7.940s	15.007s	743.130us	7	7	100.00
V2S	sec_cm_instruction_mem_integrity	acc_imem_err	4.040s	9.567s	78.390us	4	4	100.00
V2S	sec_cm_bus_integrity	acc_tl_intg_err	5.650s	9.860s	234.586us	6	6	100.00
V2S	sec_cm_controller_fsm_global_esc	acc_escalate	14.450s	20.889s	638.602us	21	22	95.45
V2S	sec_cm_controller_fsm_local_esc	acc_imem_err	4.040s	9.567s	78.390us	4	4	100.00
		acc_dmem_err	7.940s	15.007s	743.130us	7	7	100.00
		acc_zero_state_err_urnd	2.660s	8.592s	30.941us	5	5	100.00
		acc_illegal_mem_acc	2.890s	8.239s	102.327us	5	5	100.00
		acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_scramble_ctrl_fsm_local_esc	acc_imem_err	4.040s	9.567s	78.390us	4	4	100.00
		acc_dmem_err	7.940s	15.007s	743.130us	7	7	100.00
		acc_zero_state_err_urnd	2.660s	8.592s	30.941us	5	5	100.00
		acc_illegal_mem_acc	2.890s	8.239s	102.327us	5	5	100.00
		acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	acc_escalate	14.450s	20.889s	638.602us	21	22	95.45
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	acc_imem_err	4.040s	9.567s	78.390us	4	4	100.00
		acc_dmem_err	7.940s	15.007s	743.130us	7	7	100.00
		acc_zero_state_err_urnd	2.660s	8.592s	30.941us	5	5	100.00
		acc_illegal_mem_acc	2.890s	8.239s	102.327us	5	5	100.00
		acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_ctrl_redun	acc_ctrl_redun	4.020s	10.207s	55.469us	13	13	100.00
V2S	sec_cm_pc_ctrl_flow_redun	acc_pc_ctrl_flow_redun	1.900s	7.505s	21.868us	3	3	100.00
V2S	sec_cm_rnd_bus_consistency	acc_rnd_sec_cm	1.978m	2.196m	2.166ms	7	7	100.00
V2S	sec_cm_rnd_rng_digest	acc_rnd_sec_cm	1.978m	2.196m	2.166ms	7	7	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	acc_rf_base_intg_err	3.190s	8.632s	94.334us	7	7	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	acc_rf_bignum_intg_err	16.980s	23.708s	152.726us	14	14	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	acc_stack_addr_integ_chk	13.940s	20.108s	552.562us	8	8	100.00
V2S	sec_cm_call_stack_addr_integrity	acc_stack_addr_integ_chk	13.940s	20.108s	552.562us	8	8	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	acc_sec_wipe_err	12.330s	17.973s	192.313us	4	7	57.14
V2S	sec_cm_data_mem_sec_wipe	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_instruction_mem_sec_wipe	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_data_reg_sw_sec_wipe	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_write_mem_integrity	acc_multi	7.352m	8.094m	6.344ms	11	11	100.00
V2S	sec_cm_ctrl_flow_count	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_ctrl_flow_sca	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_data_mem_sw_noaccess	acc_sw_no_acc	15.160s	22.004s	756.714us	5	5	100.00
V2S	sec_cm_key_sideload	acc_single	14.260s	23.649s	373.523us	61	62	98.39
V2S	sec_cm_tlul_fifo_ctr_redun	acc_sec_cm	1.470m	1.667m	7.822ms	5	5	100.00
V2S		TOTAL				135	140	96.43
V3	stress_all_with_rand_reset	acc_stress_all_with_rand_reset	1.201m	1.478m	2.288ms	1	4	25.00
V3		TOTAL				1	4	25.00
		TOTAL				410	421	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	21	21	18	85.71
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.96	92.24	93.87	95.95	89.13	92.75	96.73	97.05

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• Offending '(model_insn_cnt_i == insn_cnt_i)' has 3 failures:

  • Test acc_sec_wipe_err has 3 failures.

    • 1.acc_sec_wipe_err.98062232032843993496635689214726131642420667838199288315447059153541177635313
      Line 115, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/1.acc_sec_wipe_err/latest/run.log

            Offending '(model_insn_cnt_i == insn_cnt_i)'
        UVM_ERROR @ 192313129 ps: (acc_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @ 192313129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 2.acc_sec_wipe_err.115710997516259889088306479264246476104123502549871315796086993444902044906719
      Line 113, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/2.acc_sec_wipe_err/latest/run.log

            Offending '(model_insn_cnt_i == insn_cnt_i)'
        UVM_ERROR @ 128570926 ps: (acc_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @ 128570926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_ERROR (acc_scoreboard.sv:320) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register acc_reg_block.status has 2 failures:

  • Test acc_escalate has 1 failures.

    • 1.acc_escalate.94533863228045162614999650808619238612500629236541674197195332070879893202797
      Line 107, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/1.acc_escalate/latest/run.log

        UVM_ERROR @   7708142 ps: (acc_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (4 [0x4] vs 255 [0xff]) value for register acc_reg_block.status
        UVM_INFO @   7708142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test acc_partial_wipe has 1 failures.

    • 6.acc_partial_wipe.35752757174895324366635498302489940409341293217295516493497999277824886632657
      Line 108, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/6.acc_partial_wipe/latest/run.log

        UVM_ERROR @   3327953 ps: (acc_scoreboard.sv:320) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_read_data.val (255 [0xff] vs 1 [0x1]) value for register acc_reg_block.status
        UVM_INFO @   3327953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1237) [acc_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test acc_stress_all_with_rand_reset has 2 failures.

    • 1.acc_stress_all_with_rand_reset.71190066149009567976561848082343888762105221132220198167083637250705249483475
      Line 163, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/1.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 113476601 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 113476601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.acc_stress_all_with_rand_reset.50230845681586754895879504395558890564686044962739589848699720634911817220569
      Line 188, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/3.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 411064930 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 411064930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:430) [acc_single_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (* [*] vs * [*]) has 1 failures:

  • Test acc_stress_all has 1 failures.

    • 1.acc_stress_all.107460418074975328012877322765777265387717154008221206714269851223862556228734
      Line 195, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/1.acc_stress_all/latest/run.log

        UVM_FATAL @ 1321125761 ps: (acc_base_vseq.sv:430) [uvm_test_top.env.virtual_sequencer.acc_single_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (16852 [0x41d4] vs 16820 [0x41b4])
        UVM_INFO @ 1321125761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:349) [acc_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 2.acc_stress_all_with_rand_reset.16957499771133241376951095353189806715039331926528690082946557000802118566358
      Line 186, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/2.acc_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 372675358 ps: (acc_base_vseq.sv:349) [uvm_test_top.env.virtual_sequencer.acc_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 372675358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!err)' has 1 failures:

  • Test acc_kmac_err has 1 failures.

    • 4.acc_kmac_err.13959841380450293196218750401652280353942675644276527399160727554370399164930
      Line 112, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/4.acc_kmac_err/latest/run.log

            Offending '(!err)'
        UVM_ERROR @  49716432 ps: (acc_model_if.sv:137) [ASSERT FAILED] NoModelErrs
        UVM_INFO @  49716432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(done_o))' has 1 failures:

  • Test acc_single has 1 failures.

    • 30.acc_single.106336958166313890037643112489013153347799542733988990700693276797385185051547
      Line 113, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_pqc-sim-vcs/30.acc_single/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @ 456123699 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @ 456123699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---