ACC/STANDARD Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	acc_smoke	4.990s	11.661s	63.665us	4	4	100.00
V1	single_binary	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V1	csr_hw_reset	acc_csr_hw_reset	1.030s	5.290s	43.713us	5	5	100.00
V1	csr_rw	acc_csr_rw	1.300s	5.367s	28.835us	20	20	100.00
V1	csr_bit_bash	acc_csr_bit_bash	2.580s	6.329s	532.222us	5	5	100.00
V1	csr_aliasing	acc_csr_aliasing	1.130s	5.281s	17.117us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	acc_csr_mem_rw_with_rand_reset	3.300s	7.627s	47.748us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	acc_csr_rw	1.300s	5.367s	28.835us	20	20	100.00
		acc_csr_aliasing	1.130s	5.281s	17.117us	5	5	100.00
V1	mem_walk	acc_mem_walk	1.767m	1.839m	2.029ms	5	5	100.00
V1	mem_partial_access	acc_mem_partial_access	57.590s	1.023m	7.556ms	5	5	100.00
V1		TOTAL				112	113	99.12
V2	reset_recovery	acc_reset	9.510s	19.510s	865.512us	7	7	100.00
V2	multi_error	acc_multi_err	19.750s	44.703s	149.530us	4	4	100.00
V2	back_to_back	acc_multi	3.540m	4.025m	2.919ms	10	11	90.91
V2	stress_all	acc_stress_all	38.500s	54.140s	406.178us	16	17	94.12
V2	lc_escalation	acc_escalate	1.078m	1.261m	1.900ms	21	21	100.00
V2	zero_state_err_urnd	acc_zero_state_err_urnd	2.080s	8.971s	20.512us	5	5	100.00
V2	sw_errs_fatal_chk	acc_sw_errs_fatal_chk	15.030s	24.097s	928.732us	10	10	100.00
V2	alert_test	acc_alert_test	1.070s	5.362s	26.383us	3	3	100.00
V2	intr_test	acc_intr_test	1.030s	5.290s	24.204us	3	3	100.00
V2	tl_d_oob_addr_access	acc_tl_errors	2.060s	6.373s	68.815us	3	3	100.00
V2	tl_d_illegal_access	acc_tl_errors	2.060s	6.373s	68.815us	3	3	100.00
V2	tl_d_outstanding_access	acc_csr_hw_reset	1.030s	5.290s	43.713us	5	5	100.00
		acc_csr_rw	1.300s	5.367s	28.835us	20	20	100.00
		acc_csr_aliasing	1.130s	5.281s	17.117us	5	5	100.00
		acc_same_csr_outstanding	1.170s	5.380s	31.135us	20	20	100.00
V2	tl_d_partial_access	acc_csr_hw_reset	1.030s	5.290s	43.713us	5	5	100.00
		acc_csr_rw	1.300s	5.367s	28.835us	20	20	100.00
		acc_csr_aliasing	1.130s	5.281s	17.117us	5	5	100.00
		acc_same_csr_outstanding	1.170s	5.380s	31.135us	20	20	100.00
V2		TOTAL				102	104	98.08
V2S	mem_integrity	acc_imem_err	4.090s	13.871s	22.216us	7	7	100.00
		acc_dmem_err	14.650s	28.756s	2.455ms	8	8	100.00
V2S	internal_integrity	acc_alu_bignum_mod_err	7.380s	19.857s	70.484us	8	8	100.00
		acc_controller_ispr_rdata_err	3.710s	14.929s	117.034us	8	8	100.00
		acc_mac_bignum_acc_err	4.470s	15.745s	75.907us	7	8	87.50
		acc_urnd_err	4.050s	14.260s	32.695us	3	3	100.00
V2S	kmac_error	acc_kmac_err				0	0	--
V2S	illegal_bus_access	acc_illegal_mem_acc	2.090s	10.939s	85.658us	8	8	100.00
V2S	acc_mem_gnt_acc_err	acc_mem_gnt_acc_err	2.290s	12.851s	26.879us	5	5	100.00
V2S	acc_non_sec_partial_wipe	acc_partial_wipe	2.500s	13.055s	263.520us	8	8	100.00
V2S	tl_intg_err	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
		acc_tl_intg_err	5.680s	10.366s	600.127us	7	7	100.00
V2S	passthru_mem_tl_intg_err	acc_passthru_mem_tl_intg_err	31.740s	36.597s	187.159us	4	4	100.00
V2S	prim_fsm_check	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	prim_count_check	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_mem_scramble	acc_smoke	4.990s	11.661s	63.665us	4	4	100.00
V2S	sec_cm_data_mem_integrity	acc_dmem_err	14.650s	28.756s	2.455ms	8	8	100.00
V2S	sec_cm_instruction_mem_integrity	acc_imem_err	4.090s	13.871s	22.216us	7	7	100.00
V2S	sec_cm_bus_integrity	acc_tl_intg_err	5.680s	10.366s	600.127us	7	7	100.00
V2S	sec_cm_controller_fsm_global_esc	acc_escalate	1.078m	1.261m	1.900ms	21	21	100.00
V2S	sec_cm_controller_fsm_local_esc	acc_imem_err	4.090s	13.871s	22.216us	7	7	100.00
		acc_dmem_err	14.650s	28.756s	2.455ms	8	8	100.00
		acc_zero_state_err_urnd	2.080s	8.971s	20.512us	5	5	100.00
		acc_illegal_mem_acc	2.090s	10.939s	85.658us	8	8	100.00
		acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_controller_fsm_sparse	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_scramble_key_sideload	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_scramble_ctrl_fsm_local_esc	acc_imem_err	4.090s	13.871s	22.216us	7	7	100.00
		acc_dmem_err	14.650s	28.756s	2.455ms	8	8	100.00
		acc_zero_state_err_urnd	2.080s	8.971s	20.512us	5	5	100.00
		acc_illegal_mem_acc	2.090s	10.939s	85.658us	8	8	100.00
		acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	acc_escalate	1.078m	1.261m	1.900ms	21	21	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	acc_imem_err	4.090s	13.871s	22.216us	7	7	100.00
		acc_dmem_err	14.650s	28.756s	2.455ms	8	8	100.00
		acc_zero_state_err_urnd	2.080s	8.971s	20.512us	5	5	100.00
		acc_illegal_mem_acc	2.090s	10.939s	85.658us	8	8	100.00
		acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_data_reg_sw_sca	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_ctrl_redun	acc_ctrl_redun	2.260s	14.482s	17.663us	10	10	100.00
V2S	sec_cm_pc_ctrl_flow_redun	acc_pc_ctrl_flow_redun	2.950s	13.097s	90.058us	3	3	100.00
V2S	sec_cm_rnd_bus_consistency	acc_rnd_sec_cm	25.990s	36.577s	813.744us	7	7	100.00
V2S	sec_cm_rnd_rng_digest	acc_rnd_sec_cm	25.990s	36.577s	813.744us	7	7	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	acc_rf_base_intg_err	3.470s	17.644s	39.445us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	acc_rf_bignum_intg_err	3.600s	18.717s	230.783us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_loop_stack_ctr_redun	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S	sec_cm_loop_stack_addr_integrity	acc_stack_addr_integ_chk	7.790s	16.260s	51.946us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	acc_stack_addr_integ_chk	7.790s	16.260s	51.946us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	acc_sec_wipe_err	1.770s	13.023s	12.835us	2	3	66.67
V2S	sec_cm_data_mem_sec_wipe	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_instruction_mem_sec_wipe	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_data_reg_sw_sec_wipe	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_write_mem_integrity	acc_multi	3.540m	4.025m	2.919ms	10	11	90.91
V2S	sec_cm_ctrl_flow_count	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_ctrl_flow_sca	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_data_mem_sw_noaccess	acc_sw_no_acc	55.700s	1.149m	872.650us	6	6	100.00
V2S	sec_cm_key_sideload	acc_single	24.630s	33.759s	322.621us	43	44	97.73
V2S	sec_cm_tlul_fifo_ctr_redun	acc_sec_cm	1.436m	1.600m	14.949ms	5	5	100.00
V2S		TOTAL				131	133	98.50
V3	stress_all_with_rand_reset	acc_stress_all_with_rand_reset	3.660m	4.055m	4.017ms	2	4	50.00
V3		TOTAL				2	4	50.00
		TOTAL				347	354	98.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	9	81.82
V2S	21	20	18	85.71
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.87	91.25	95.12	98.36	87.50	97.15	97.01	97.67

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• Offending '(!$isunknown(done_o))' has 2 failures:

  • Test acc_multi has 1 failures.

    • 3.acc_multi.97972711308923483425850792443441560837175132722951593594431345545582438019224
      Line 175, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/3.acc_multi/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @ 253813460 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @ 253813460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test acc_mac_bignum_acc_err has 1 failures.

    • 7.acc_mac_bignum_acc_err.40768262797523353108810279880821083932979556109521398993526292150432896094417
      Line 118, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/7.acc_mac_bignum_acc_err/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @  23764100 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @  23764100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_scoreboard.sv:547) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 2 failures:

  • Test acc_stress_all has 1 failures.

    • 11.acc_stress_all.31208871404884696820509041200195428915432444481593890610465616824465036945422
      Line 161, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/11.acc_stress_all/latest/run.log

        UVM_FATAL @ 209676063 ps: (acc_scoreboard.sv:547) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @ 209676063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test acc_single has 1 failures.

    • 22.acc_single.39871275520315510798511537005071960957958113434533553628735154588195891103992
      Line 111, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/22.acc_single/latest/run.log

        UVM_FATAL @  83150694 ps: (acc_scoreboard.sv:547) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @  83150694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1237) [acc_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 1.acc_stress_all_with_rand_reset.93201877335286923394707623751699111417294685976873774244682250734246450288719
      Line 482, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/1.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 983267677 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 983267677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(model_insn_cnt_i == insn_cnt_i)' has 1 failures:

  • Test acc_sec_wipe_err has 1 failures.

    • 1.acc_sec_wipe_err.45248710340623714426948337487610187293590321388992765041162521561924311630074
      Line 125, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/1.acc_sec_wipe_err/latest/run.log

            Offending '(model_insn_cnt_i == insn_cnt_i)'
        UVM_ERROR @  12834592 ps: (acc_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  12834592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:349) [acc_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 2.acc_stress_all_with_rand_reset.8112584775696223846056926623966890510777751901090079461519750985004695209312
      Line 193, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/acc_standard-sim-vcs/2.acc_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 710156256 ps: (acc_base_vseq.sv:349) [uvm_test_top.env.virtual_sequencer.acc_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 710156256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---