ADC_CTRL Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	1.750s	5.420s	5.777ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.720s	5.290s	869.862us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.420s	4.533s	543.612us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.059m	1.121m	52.802ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.880s	6.064s	976.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.500s	5.592s	543.408us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.420s	4.533s	543.612us	20	20	100.00
		adc_ctrl_csr_aliasing	2.880s	6.064s	976.477us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	filters_polled	adc_ctrl_filters_polled	9.253m	9.307m	325.639ms	5	5	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	52.720s	56.096s	164.790ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	12.407m	12.469m	499.672ms	11	11	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	2.704m	2.769m	488.945ms	3	3	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	12.999m	13.055m	537.841ms	19	19	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	5.359m	5.422m	201.752ms	3	3	100.00
V2	filters_both	adc_ctrl_filters_both	14.862m	14.928m	573.487ms	26	26	100.00
V2	clock_gating	adc_ctrl_clock_gating	14.149m	14.207m	542.879ms	10	11	90.91
V2	poweron_counter	adc_ctrl_poweron_counter	1.970s	5.342s	3.689ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	42.720s	45.830s	30.949ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.798m	3.859m	134.143ms	8	8	100.00
V2	stress_all	adc_ctrl_stress_all	14.703m	14.758m	600.013ms	17	17	100.00
V2	alert_test	adc_ctrl_alert_test	1.120s	5.058s	474.290us	3	3	100.00
V2	intr_test	adc_ctrl_intr_test	1.240s	4.569s	504.032us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.880s	5.267s	474.000us	3	3	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.880s	5.267s	474.000us	3	3	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.720s	5.290s	869.862us	5	5	100.00
		adc_ctrl_csr_rw	1.420s	4.533s	543.612us	20	20	100.00
		adc_ctrl_csr_aliasing	2.880s	6.064s	976.477us	5	5	100.00
		adc_ctrl_same_csr_outstanding	3.730s	7.431s	2.522ms	3	3	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.720s	5.290s	869.862us	5	5	100.00
		adc_ctrl_csr_rw	1.420s	4.533s	543.612us	20	20	100.00
		adc_ctrl_csr_aliasing	2.880s	6.064s	976.477us	5	5	100.00
		adc_ctrl_same_csr_outstanding	3.730s	7.431s	2.522ms	3	3	100.00
V2		TOTAL				164	165	99.39
V2S	tl_intg_err	adc_ctrl_sec_cm	12.280s	15.359s	8.064ms	3	3	100.00
		adc_ctrl_tl_intg_err	15.230s	18.287s	8.954ms	4	4	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	15.230s	18.287s	8.954ms	4	4	100.00
V2S		TOTAL				7	7	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	12.120s	15.430s	88.731ms	14	14	100.00
V3		TOTAL				14	14	100.00
		TOTAL				241	242	99.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.41	99.05	96.03	100.00	100.00	98.64	95.95	92.21

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:259) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 9.adc_ctrl_clock_gating.115283313982125977467857823298715267969327028354689382462384540391640837923411
      Line 323, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/adc_ctrl-sim-vcs/9.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 5392939655 ps: (cip_base_scoreboard.sv:259) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 5392939655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---