AES/MASKED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 1.910s 11.817s 632.887us 1 1 100.00
V1 smoke aes_smoke 1.210s 5.718s 216.216us 1 1 100.00
V1 csr_hw_reset aes_csr_hw_reset 0.640s 4.853s 96.248us 5 5 100.00
V1 csr_rw aes_csr_rw 0.700s 4.918s 78.880us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 4.940s 8.646s 1.655ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 1.530s 5.994s 407.402us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 0.990s 4.880s 84.536us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 0.700s 4.918s 78.880us 20 20 100.00
aes_csr_aliasing 1.530s 5.994s 407.402us 5 5 100.00
V1 TOTAL 40 40 100.00
V2 algorithm aes_smoke 1.210s 5.718s 216.216us 1 1 100.00
aes_config_error 2.750s 7.933s 968.352us 12 12 100.00
aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2 key_length aes_smoke 1.210s 5.718s 216.216us 1 1 100.00
aes_config_error 2.750s 7.933s 968.352us 12 12 100.00
aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2 back2back aes_stress 2.430s 5.863s 303.722us 4 4 100.00
aes_b2b 8.530s 12.495s 631.558us 4 4 100.00
V2 backpressure aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2 multi_message aes_smoke 1.210s 5.718s 216.216us 1 1 100.00
aes_config_error 2.750s 7.933s 968.352us 12 12 100.00
aes_stress 2.430s 5.863s 303.722us 4 4 100.00
aes_alert_reset 11.320s 15.973s 1.338ms 8 8 100.00
V2 failure_test aes_man_cfg_err 0.680s 5.726s 61.531us 1 1 100.00
aes_config_error 2.750s 7.933s 968.352us 12 12 100.00
aes_alert_reset 11.320s 15.973s 1.338ms 8 8 100.00
V2 trigger_clear_test aes_clear 3.690s 7.941s 117.517us 5 5 100.00
V2 nist_test_vectors aes_nist_vectors 7.830s 11.447s 287.911us 3 3 100.00
V2 reset_recovery aes_alert_reset 11.320s 15.973s 1.338ms 8 8 100.00
V2 stress aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2 sideload aes_stress 2.430s 5.863s 303.722us 4 4 100.00
aes_sideload 2.000s 6.990s 80.158us 4 4 100.00
V2 deinitialization aes_deinit 3.600s 8.025s 159.077us 3 3 100.00
V2 stress_all aes_stress_all 37.340s 40.453s 1.431ms 5 5 100.00
V2 alert_test aes_alert_test 0.590s 4.333s 56.380us 3 3 100.00
V2 tl_d_oob_addr_access aes_tl_errors 2.000s 6.166s 379.658us 4 4 100.00
V2 tl_d_illegal_access aes_tl_errors 2.000s 6.166s 379.658us 4 4 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 0.640s 4.853s 96.248us 5 5 100.00
aes_csr_rw 0.700s 4.918s 78.880us 20 20 100.00
aes_csr_aliasing 1.530s 5.994s 407.402us 5 5 100.00
aes_same_csr_outstanding 1.080s 5.029s 87.433us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 0.640s 4.853s 96.248us 5 5 100.00
aes_csr_rw 0.700s 4.918s 78.880us 20 20 100.00
aes_csr_aliasing 1.530s 5.994s 407.402us 5 5 100.00
aes_same_csr_outstanding 1.080s 5.029s 87.433us 20 20 100.00
V2 TOTAL 76 76 100.00
V2S reseeding aes_reseed 5.230s 8.443s 170.555us 5 5 100.00
V2S fault_inject aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_control_fi_walk 1.060m 1.060m 440 441 99.77
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
aes_cipher_fi_walk 2.370s 6.038s 425.698us 546 546 100.00
aes_core_fi_walk 5.340s 9.475s 925.202us 35 35 100.00
V2S shadow_reg_update_error aes_shadow_reg_errors 0.740s 4.842s 76.410us 3 3 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 0.740s 4.842s 76.410us 3 3 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 0.740s 4.842s 76.410us 3 3 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 0.740s 4.842s 76.410us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 1.360s 6.106s 94.114us 3 3 100.00
V2S tl_intg_err aes_sec_cm 2.410s 6.017s 1.501ms 3 3 100.00
aes_tl_intg_err 2.030s 6.267s 1.120ms 8 8 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 2.030s 6.267s 1.120ms 8 8 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 11.320s 15.973s 1.338ms 8 8 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 0.740s 4.842s 76.410us 3 3 100.00
V2S sec_cm_main_config_sparse aes_smoke 1.210s 5.718s 216.216us 1 1 100.00
aes_stress 2.430s 5.863s 303.722us 4 4 100.00
aes_alert_reset 11.320s 15.973s 1.338ms 8 8 100.00
aes_core_fi 2.340s 6.126s 762.787us 39 39 100.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 0.740s 4.842s 76.410us 3 3 100.00
V2S sec_cm_aux_config_regwen aes_readability 0.670s 5.716s 181.406us 1 1 100.00
aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2S sec_cm_key_sideload aes_stress 2.430s 5.863s 303.722us 4 4 100.00
aes_sideload 2.000s 6.990s 80.158us 4 4 100.00
V2S sec_cm_key_sw_unreadable aes_readability 0.670s 5.716s 181.406us 1 1 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 0.670s 5.716s 181.406us 1 1 100.00
V2S sec_cm_key_sec_wipe aes_readability 0.670s 5.716s 181.406us 1 1 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 0.670s 5.716s 181.406us 1 1 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 0.670s 5.716s 181.406us 1 1 100.00
V2S sec_cm_data_reg_key_sca aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2S sec_cm_key_masking aes_stress 2.430s 5.863s 303.722us 4 4 100.00
V2S sec_cm_main_fsm_sparse aes_fi 2.260s 7.041s 138.453us 4 4 100.00
V2S sec_cm_main_fsm_redun aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
aes_ctr_fi 2.390s 6.078s 1.255ms 18 18 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 2.260s 7.041s 138.453us 4 4 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
V2S sec_cm_ctr_fsm_sparse aes_fi 2.260s 7.041s 138.453us 4 4 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_ctr_fi 2.390s 6.078s 1.255ms 18 18 100.00
V2S sec_cm_ctrl_sparse aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
aes_ctr_fi 2.390s 6.078s 1.255ms 18 18 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 11.320s 15.973s 1.338ms 8 8 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
aes_ctr_fi 2.390s 6.078s 1.255ms 18 18 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
aes_ctr_fi 2.390s 6.078s 1.255ms 18 18 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_ctr_fi 2.390s 6.078s 1.255ms 18 18 100.00
V2S sec_cm_data_reg_local_esc aes_fi 2.260s 7.041s 138.453us 4 4 100.00
aes_control_fi 1.690s 5.826s 733.195us 274 274 100.00
aes_cipher_fi 1.540s 5.754s 515.884us 305 305 100.00
V2S TOTAL 1684 1685 99.94
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1800 1801 99.94

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 14 14 13 92.86
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.20 99.63 97.41 100.00 100.00 99.68 98.38 99.29

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22

Failure Buckets