AES/UNMASKED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 0.580s 4.622s 94.593us 1 1 100.00
V1 smoke aes_smoke 0.870s 4.616s 149.748us 1 1 100.00
V1 csr_hw_reset aes_csr_hw_reset 0.560s 4.906s 75.068us 5 5 100.00
V1 csr_rw aes_csr_rw 0.690s 4.935s 62.554us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 4.630s 8.511s 1.219ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 2.070s 5.618s 834.708us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 1.250s 5.074s 261.802us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 0.690s 4.935s 62.554us 20 20 100.00
aes_csr_aliasing 2.070s 5.618s 834.708us 5 5 100.00
V1 TOTAL 57 57 100.00
V2 algorithm aes_smoke 0.870s 4.616s 149.748us 1 1 100.00
aes_config_error 1.480s 5.248s 312.119us 13 13 100.00
aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2 key_length aes_smoke 0.870s 4.616s 149.748us 1 1 100.00
aes_config_error 1.480s 5.248s 312.119us 13 13 100.00
aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2 back2back aes_stress 1.460s 5.246s 193.371us 4 4 100.00
aes_b2b 3.340s 7.195s 109.550us 3 3 100.00
V2 backpressure aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2 multi_message aes_smoke 0.870s 4.616s 149.748us 1 1 100.00
aes_config_error 1.480s 5.248s 312.119us 13 13 100.00
aes_stress 1.460s 5.246s 193.371us 4 4 100.00
aes_alert_reset 1.540s 5.243s 249.125us 7 7 100.00
V2 failure_test aes_man_cfg_err 0.700s 4.638s 85.736us 3 3 100.00
aes_config_error 1.480s 5.248s 312.119us 13 13 100.00
aes_alert_reset 1.540s 5.243s 249.125us 7 7 100.00
V2 trigger_clear_test aes_clear 1.520s 5.168s 110.170us 4 4 100.00
V2 nist_test_vectors aes_nist_vectors 2.220s 5.781s 284.237us 1 1 100.00
V2 reset_recovery aes_alert_reset 1.540s 5.243s 249.125us 7 7 100.00
V2 stress aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2 sideload aes_stress 1.460s 5.246s 193.371us 4 4 100.00
aes_sideload 1.190s 5.122s 115.211us 4 4 100.00
V2 deinitialization aes_deinit 0.800s 4.563s 269.570us 1 1 100.00
V2 stress_all aes_stress_all 8.260s 12.572s 341.598us 5 5 100.00
V2 alert_test aes_alert_test 0.700s 5.017s 55.221us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 1.780s 5.794s 219.776us 4 4 100.00
V2 tl_d_illegal_access aes_tl_errors 1.780s 5.794s 219.776us 4 4 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 0.560s 4.906s 75.068us 5 5 100.00
aes_csr_rw 0.690s 4.935s 62.554us 20 20 100.00
aes_csr_aliasing 2.070s 5.618s 834.708us 5 5 100.00
aes_same_csr_outstanding 0.940s 5.060s 243.468us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 0.560s 4.906s 75.068us 5 5 100.00
aes_csr_rw 0.690s 4.935s 62.554us 20 20 100.00
aes_csr_aliasing 2.070s 5.618s 834.708us 5 5 100.00
aes_same_csr_outstanding 0.940s 5.060s 243.468us 20 20 100.00
V2 TOTAL 119 119 100.00
V2S reseeding aes_reseed 1.360s 5.157s 187.025us 3 3 100.00
V2S fault_inject aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_control_fi_walk 1.560s 5.888s 1.269ms 441 441 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
aes_cipher_fi_walk 1.650s 5.865s 1.658ms 546 546 100.00
aes_core_fi_walk 1.410s 5.388s 188.509us 35 35 100.00
V2S shadow_reg_update_error aes_shadow_reg_errors 0.800s 4.535s 84.822us 3 3 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 0.800s 4.535s 84.822us 3 3 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 0.800s 4.535s 84.822us 3 3 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 0.800s 4.535s 84.822us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 1.240s 4.871s 92.087us 3 3 100.00
V2S tl_intg_err aes_sec_cm 1.990s 5.291s 573.877us 3 3 100.00
aes_tl_intg_err 1.630s 5.704s 153.996us 10 10 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 1.630s 5.704s 153.996us 10 10 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 1.540s 5.243s 249.125us 7 7 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 0.800s 4.535s 84.822us 3 3 100.00
V2S sec_cm_main_config_sparse aes_smoke 0.870s 4.616s 149.748us 1 1 100.00
aes_stress 1.460s 5.246s 193.371us 4 4 100.00
aes_alert_reset 1.540s 5.243s 249.125us 7 7 100.00
aes_core_fi 1.000s 5.161s 386.879us 31 31 100.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 0.800s 4.535s 84.822us 3 3 100.00
V2S sec_cm_aux_config_regwen aes_readability 0.670s 4.627s 67.372us 3 3 100.00
aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2S sec_cm_key_sideload aes_stress 1.460s 5.246s 193.371us 4 4 100.00
aes_sideload 1.190s 5.122s 115.211us 4 4 100.00
V2S sec_cm_key_sw_unreadable aes_readability 0.670s 4.627s 67.372us 3 3 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 0.670s 4.627s 67.372us 3 3 100.00
V2S sec_cm_key_sec_wipe aes_readability 0.670s 4.627s 67.372us 3 3 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 0.670s 4.627s 67.372us 3 3 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 0.670s 4.627s 67.372us 3 3 100.00
V2S sec_cm_data_reg_key_sca aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2S sec_cm_key_masking aes_stress 1.460s 5.246s 193.371us 4 4 100.00
V2S sec_cm_main_fsm_sparse aes_fi 1.400s 5.155s 111.661us 5 5 100.00
V2S sec_cm_main_fsm_redun aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
aes_ctr_fi 0.840s 4.944s 74.762us 19 19 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 1.400s 5.155s 111.661us 5 5 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
V2S sec_cm_ctr_fsm_sparse aes_fi 1.400s 5.155s 111.661us 5 5 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_ctr_fi 0.840s 4.944s 74.762us 19 19 100.00
V2S sec_cm_ctrl_sparse aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
aes_ctr_fi 0.840s 4.944s 74.762us 19 19 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 1.540s 5.243s 249.125us 7 7 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
aes_ctr_fi 0.840s 4.944s 74.762us 19 19 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
aes_ctr_fi 0.840s 4.944s 74.762us 19 19 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_ctr_fi 0.840s 4.944s 74.762us 19 19 100.00
V2S sec_cm_data_reg_local_esc aes_fi 1.400s 5.155s 111.661us 5 5 100.00
aes_control_fi 1.680s 5.925s 182.710us 272 272 100.00
aes_cipher_fi 1.590s 5.904s 895.624us 206 206 100.00
V2S TOTAL 1580 1580 100.00
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1756 1756 100.00

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 14 14 14 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.49 97.44 96.57 99.73 92.68 98.41 98.11 99.50

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22