ALERT_HANDLER/DRAGONFLY Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	15.830s	19.610s	440.907us	1	1	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	4.350s	8.307s	119.565us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	5.880s	9.314s	108.258us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	2.448m	2.509m	7.390ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	3.509m	3.566m	5.203ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	8.690s	12.579s	743.416us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	5.880s	9.314s	108.258us	20	20	100.00
		alert_handler_csr_aliasing	3.509m	3.566m	5.203ms	5	5	100.00
V1		TOTAL				56	56	100.00
V2	esc_accum	alert_handler_esc_alert_accum	1.944m	1.999m	13.821ms	1	1	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	25.240s	28.659s	1.281ms	4	4	100.00
V2	entropy	alert_handler_entropy	31.794m	31.858m	111.075ms	7	7	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	43.220s	47.004s	1.217ms	9	9	100.00
V2	clk_skew	alert_handler_smoke	15.830s	19.610s	440.907us	1	1	100.00
V2	random_alerts	alert_handler_random_alerts	29.330s	32.941s	835.874us	3	3	100.00
V2	random_classes	alert_handler_random_classes	38.990s	42.520s	2.343ms	3	3	100.00
V2	ping_timeout	alert_handler_ping_timeout	6.259m	6.311m	106.844ms	16	19	84.21
V2	lpg	alert_handler_lpg	33.042m	33.095m	857.274ms	14	14	100.00
		alert_handler_lpg_stub_clk	22.404m	22.456m	39.040ms	4	4	100.00
V2	stress_all	alert_handler_stress_all	45.275m	45.338m	80.088ms	18	18	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	26.450s	29.720s	1.250ms	3	3	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	2.500s	6.185s	42.284us	6	6	100.00
V2	intr_test	alert_handler_intr_test	1.150s	5.040s	11.436us	5	5	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	21.210s	24.437s	1.539ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	21.210s	24.437s	1.539ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	4.350s	8.307s	119.565us	5	5	100.00
		alert_handler_csr_rw	5.880s	9.314s	108.258us	20	20	100.00
		alert_handler_csr_aliasing	3.509m	3.566m	5.203ms	5	5	100.00
		alert_handler_same_csr_outstanding	33.920s	37.671s	5.681ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	4.350s	8.307s	119.565us	5	5	100.00
		alert_handler_csr_rw	5.880s	9.314s	108.258us	20	20	100.00
		alert_handler_csr_aliasing	3.509m	3.566m	5.203ms	5	5	100.00
		alert_handler_same_csr_outstanding	33.920s	37.671s	5.681ms	20	20	100.00
V2		TOTAL				133	136	97.79
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	4.449m	4.509m	11.955ms	11	11	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	4.449m	4.509m	11.955ms	11	11	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	4.449m	4.509m	11.955ms	11	11	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	4.449m	4.509m	11.955ms	11	11	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	11.240m	11.304m	59.064ms	12	12	100.00
V2S	tl_intg_err	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
		alert_handler_tl_intg_err	1.015m	1.073m	5.772ms	25	25	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.015m	1.073m	5.772ms	25	25	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	4.449m	4.509m	11.955ms	11	11	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	15.830s	19.610s	440.907us	1	1	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	15.830s	19.610s	440.907us	1	1	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	15.830s	19.610s	440.907us	1	1	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	15.830s	19.610s	440.907us	1	1	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	43.220s	47.004s	1.217ms	9	9	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	33.042m	33.095m	857.274ms	14	14	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	43.220s	47.004s	1.217ms	9	9	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	31.794m	31.858m	111.075ms	7	7	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	31.794m	31.858m	111.075ms	7	7	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	17.280s	21.204s	5.423ms	4	4	100.00
V2S		TOTAL				52	52	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	3.960m	4.014m	6.742ms	12	13	92.31
V3		TOTAL				12	13	92.31
		TOTAL				253	257	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.21	99.99	98.65	97.37	100.00	99.99	98.92	99.51

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 3 failures:
  • Test alert_handler_ping_timeout has 3 failures.

    • 12.alert_handler_ping_timeout.36635299663636654781590524852009490958930960282334225119212360841738400046194
      Line 120, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_dragonfly-sim-vcs/12.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 5684139280 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
        UVM_INFO @ 5684139280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.alert_handler_ping_timeout.3258613618499939582151414536434716293507767722423192607462124806826520829697
      Line 128, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_dragonfly-sim-vcs/16.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 20504102295 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 2 [0x2]) reg name: intr_state
        UVM_INFO @ 20504102295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 12.alert_handler_stress_all_with_rand_reset.61451515083570172642106883535799921425927251346827308813072306457334490478765
      Line 130, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_dragonfly-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9736486025 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9736486025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---