ALERT_HANDLER/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	15.920s	19.696s	421.613us	1	1	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	5.100s	8.145s	394.283us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	5.430s	9.376s	208.451us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	4.634m	4.690m	8.818ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	1.079m	1.129m	1.726ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.010s	10.541s	342.026us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	5.430s	9.376s	208.451us	20	20	100.00
		alert_handler_csr_aliasing	1.079m	1.129m	1.726ms	5	5	100.00
V1		TOTAL				56	56	100.00
V2	esc_accum	alert_handler_esc_alert_accum	1.849m	1.911m	3.508ms	1	1	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	31.030s	34.302s	970.139us	3	3	100.00
V2	entropy	alert_handler_entropy	18.905m	18.967m	161.844ms	10	10	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	29.630s	33.064s	921.208us	10	10	100.00
V2	clk_skew	alert_handler_smoke	15.920s	19.696s	421.613us	1	1	100.00
V2	random_alerts	alert_handler_random_alerts	19.420s	23.764s	3.392ms	1	1	100.00
V2	random_classes	alert_handler_random_classes	24.830s	29.547s	7.877ms	4	4	100.00
V2	ping_timeout	alert_handler_ping_timeout	6.867m	6.922m	70.024ms	12	13	92.31
V2	lpg	alert_handler_lpg	27.566m	27.630m	224.877ms	12	12	100.00
		alert_handler_lpg_stub_clk	12.998m	13.056m	69.892ms	4	4	100.00
V2	stress_all	alert_handler_stress_all	36.679m	36.735m	278.140ms	21	21	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	28.170s	31.545s	2.325ms	3	3	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	2.090s	5.112s	40.050us	6	6	100.00
V2	intr_test	alert_handler_intr_test	0.980s	4.108s	15.384us	5	5	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	12.800s	16.566s	358.446us	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	12.800s	16.566s	358.446us	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	5.100s	8.145s	394.283us	5	5	100.00
		alert_handler_csr_rw	5.430s	9.376s	208.451us	20	20	100.00
		alert_handler_csr_aliasing	1.079m	1.129m	1.726ms	5	5	100.00
		alert_handler_same_csr_outstanding	25.900s	29.403s	2.632ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	5.100s	8.145s	394.283us	5	5	100.00
		alert_handler_csr_rw	5.430s	9.376s	208.451us	20	20	100.00
		alert_handler_csr_aliasing	1.079m	1.129m	1.726ms	5	5	100.00
		alert_handler_same_csr_outstanding	25.900s	29.403s	2.632ms	20	20	100.00
V2		TOTAL				132	133	99.25
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	3.362m	3.425m	5.561ms	14	14	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	3.362m	3.425m	5.561ms	14	14	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	3.362m	3.425m	5.561ms	14	14	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	3.362m	3.425m	5.561ms	14	14	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	10.851m	10.921m	16.460ms	11	11	100.00
V2S	tl_intg_err	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
		alert_handler_tl_intg_err	45.170s	48.382s	4.418ms	28	28	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	45.170s	48.382s	4.418ms	28	28	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	3.362m	3.425m	5.561ms	14	14	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	15.920s	19.696s	421.613us	1	1	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	15.920s	19.696s	421.613us	1	1	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	15.920s	19.696s	421.613us	1	1	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	15.920s	19.696s	421.613us	1	1	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	29.630s	33.064s	921.208us	10	10	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	27.566m	27.630m	224.877ms	12	12	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	29.630s	33.064s	921.208us	10	10	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	18.905m	18.967m	161.844ms	10	10	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	18.905m	18.967m	161.844ms	10	10	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	14.630s	18.219s	563.975us	6	6	100.00
V2S		TOTAL				59	59	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	4.988m	5.052m	9.545ms	7	10	70.00
V3		TOTAL				7	10	70.00
		TOTAL				254	258	98.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.16	99.99	98.80	97.06	100.00	99.99	98.88	99.40

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 7.alert_handler_stress_all_with_rand_reset.43606292040235600576978746609163151958957659922520789879144598735296207522966
      Line 125, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_egret-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6086813872 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6086813872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.alert_handler_stress_all_with_rand_reset.53620003596730830706276445385012287263764395705182608129413154528039179207555
      Line 84, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_egret-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 108567991 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 108567991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1150) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test alert_handler_stress_all_with_rand_reset has 1 failures.

    • 9.alert_handler_stress_all_with_rand_reset.4385325605913535616844687255064563135487820542952807453828269323087877692799
      Line 208, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_egret-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4078727931 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 4078727931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 1 failures:

  • Test alert_handler_ping_timeout has 1 failures.

    • 12.alert_handler_ping_timeout.106063128267039508441633232997627985859885182756499467321322138552081845178545
      Line 110, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/alert_handler_top_egret-sim-vcs/12.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 19290032646 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
        UVM_INFO @ 19290032646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---