AON_TIMER Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	0.730s	4.467s	565.850us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.180s	5.317s	717.004us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.040s	4.870s	531.947us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	7.340s	11.282s	7.293ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.080s	4.554s	501.790us	3	3	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.050s	4.754s	505.596us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.040s	4.870s	531.947us	20	20	100.00
		aon_timer_csr_aliasing	1.080s	4.554s	501.790us	3	3	100.00
V1	mem_walk	aon_timer_mem_walk	0.770s	4.467s	505.360us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.800s	4.478s	366.944us	5	5	100.00
V1		TOTAL				68	68	100.00
V2	prescaler	aon_timer_prescaler	0.690s	4.452s	525.104us	1	1	100.00
V2	jump	aon_timer_jump	1.070s	4.449s	752.985us	5	5	100.00
V2	stress_all	aon_timer_stress_all	30.240s	33.666s	84.372ms	5	5	100.00
V2	alert_test	aon_timer_alert_test	0.860s	4.299s	403.938us	3	3	100.00
V2	intr_test	aon_timer_intr_test	0.920s	5.037s	429.707us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.310s	5.758s	543.792us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.310s	5.758s	543.792us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.180s	5.317s	717.004us	5	5	100.00
		aon_timer_csr_rw	1.040s	4.870s	531.947us	20	20	100.00
		aon_timer_csr_aliasing	1.080s	4.554s	501.790us	3	3	100.00
		aon_timer_same_csr_outstanding	3.040s	6.603s	2.412ms	3	3	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.180s	5.317s	717.004us	5	5	100.00
		aon_timer_csr_rw	1.040s	4.870s	531.947us	20	20	100.00
		aon_timer_csr_aliasing	1.080s	4.554s	501.790us	3	3	100.00
		aon_timer_same_csr_outstanding	3.040s	6.603s	2.412ms	3	3	100.00
V2		TOTAL				87	87	100.00
V2S	tl_intg_err	aon_timer_sec_cm	3.110s	6.484s	4.313ms	3	3	100.00
		aon_timer_tl_intg_err	9.250s	12.521s	8.389ms	3	3	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	9.250s	12.521s	8.389ms	3	3	100.00
V2S		TOTAL				6	6	100.00
V3	max_threshold	aon_timer_smoke_max_thold	1.120s	4.388s	603.792us	5	5	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.030s	4.374s	567.174us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	6.000s	9.650s	3.517ms	3	3	100.00
V3	custom_intr	aon_timer_custom_intr	1.190s	5.232s	685.474us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	12.230s	15.972s	4.228ms	4	4	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	27.010s	30.019s	8.977ms	7	7	100.00
V3		TOTAL				34	34	100.00
		TOTAL				195	195	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	7	7	7	100.00
V2S	2	2	2	100.00
V3	6	6	6	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.57	99.09	99.05	98.04	--	98.56	96.67	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22