2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 0 | 0 | -- | |||
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 0 | 0 | -- | |||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 0 | 0 | -- | |||
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 0 | 0 | -- | |||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 4.467m | 6.784m | 294.505us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 4.467m | 6.784m | 294.505us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 4.467m | 6.784m | 294.505us | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 1.515m | 2.945m | 124.307us | 1 | 1 | 100.00 |
| chip_sw_example_manufacturer | 1.091m | 1.091m | 0 | 1 | 0.00 | |||
| chip_sw_example_concurrency | 2.571m | 8.496m | 168.617us | 1 | 1 | 100.00 | ||
| chip_sw_example_flash | 0 | 0 | -- | |||||
| chip_sw_uart_smoketest_signed | 0 | 0 | -- | |||||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 0 | -- | |||
| V1 | csr_rw | chip_csr_rw | 0 | 0 | -- | |||
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.919h | 1.963h | 12.019ms | 0 | 1 | 0.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 1.907h | 1.951h | 12.027ms | 0 | 1 | 0.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 0 | -- | |||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 1.907h | 1.951h | 12.027ms | 0 | 1 | 0.00 |
| chip_csr_rw | 0 | 0 | -- | |||||
| V1 | xbar_smoke | xbar_smoke | 20.690s | 34.333s | 64.616us | 100 | 100 | 100.00 |
| V1 | TOTAL | 105 | 108 | 97.22 | ||||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | |||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 5.270m | 9.325m | 422.019us | 0 | 5 | 0.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 3.111m | 7.021m | 204.355us | 0 | 1 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 0 | 0 | -- | |||
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 0 | 0 | -- | |||
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 0 | 0 | -- | |||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 0 | 0 | -- | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 2.570s | 19.112s | 0 | 10 | 0.00 | |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 2.570s | 19.112s | 0 | 10 | 0.00 | |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 0 | 0 | -- | |||
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 0 | 0 | -- | |||
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 0 | 0 | -- | |||
| V2 | chip_sw_mbx_smoke | chip_sw_mbx_smoke | 0 | 0 | -- | |||
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | |||
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | |||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 1.609m | 1.842m | 117.027us | 0 | 1 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 1.538m | 1.759m | 117.032us | 0 | 1 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 4.707m | 5.281m | 310.477us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 0 | -- | |||
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 0 | 0 | -- | |||
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 8.593m | 8.814m | 1.037ms | 3 | 5 | 60.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 3.539m | 5.839m | 266.178us | 1 | 1 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.381m | 8.020m | 555.585us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | |||
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.381m | 8.020m | 555.585us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 6.003m | 6.730m | 385.460us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 2.723m | 3.134m | 182.141us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 2.723m | 3.134m | 182.141us | 0 | 1 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 5.266m | 6.098m | 2.310ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 6.368m | 7.203m | 326.748us | 7 | 7 | 100.00 |
| chip_plic_all_irqs_10 | 5.391m | 6.209m | 296.504us | 7 | 7 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 2.616m | 3.316m | 164.473us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_acc_randomness | 3.916m | 4.413m | 244.560us | 1 | 1 | 100.00 |
| chip_sw_aes_idle | 2.665m | 3.282m | 165.041us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 2.718m | 3.629m | 177.854us | 1 | 1 | 100.00 | ||
| chip_sw_kmac_idle | 2.472m | 3.352m | 163.320us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 2.749m | 3.759m | 184.688us | 0 | 1 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 2.855m | 3.627m | 184.640us | 0 | 1 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 2.602m | 3.369m | 184.608us | 0 | 1 | 0.00 | ||
| chip_sw_clkmgr_off_acc_trans | 2.842m | 3.295m | 184.688us | 0 | 1 | 0.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 52.360m | 53.027m | 1.464ms | 1 | 1 | 100.00 |
| chip_sw_aes_enc_jitter_en | 2.875m | 3.574m | 172.902us | 1 | 1 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 2.740m | 3.429m | 173.685us | 1 | 1 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 4.278m | 5.219m | 304.389us | 0 | 1 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 3.106m | 4.307m | 188.566us | 1 | 1 | 100.00 | ||
| chip_sw_clkmgr_jitter | 2.504m | 3.218m | 161.186us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | |||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | |||||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 5.306m | 5.712m | 1.963ms | 1 | 1 | 100.00 |
| chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq | 1.524h | 1.532h | 20.675ms | 1 | 1 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.822m | 6.334m | 2.134ms | 1 | 1 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.828m | 6.617m | 2.143ms | 1 | 1 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 10.069m | 10.819m | 3.917ms | 0 | 1 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.365m | 7.499m | 2.355ms | 1 | 1 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 12.202m | 13.075m | 4.388ms | 1 | 1 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 48.773m | 49.676m | 14.088ms | 1 | 1 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 0 | 0 | -- | |||
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 16.608m | 19.524m | 951.284us | 87 | 100 | 87.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 5.225m | 7.982m | 519.892us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 2.723m | 3.134m | 182.141us | 0 | 1 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 5.225m | 7.982m | 519.892us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 16.608m | 19.524m | 951.284us | 87 | 100 | 87.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | |||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 4.707m | 5.281m | 310.477us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 5.957m | 8.844m | 412.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 4.529m | 7.735m | 304.371us | 1 | 1 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 5.178m | 8.908m | 343.981us | 0 | 1 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 2.599m | 5.506m | 163.486us | 1 | 1 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 16.608m | 19.524m | 951.284us | 87 | 100 | 87.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 0 | 0 | -- | |||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 16.608m | 19.524m | 951.284us | 87 | 100 | 87.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 5.178m | 8.908m | 343.981us | 0 | 1 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 5.496m | 6.017m | 423.251us | 7 | 7 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 0 | 0 | -- | |||
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 0 | -- | |||
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 0 | 0 | -- | |||
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 2.401m | 6.072m | 168.097us | 1 | 1 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 4.581m | 5.579m | 304.506us | 0 | 1 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 4.562m | 5.478m | 304.513us | 0 | 1 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 13.194m | 13.940m | 1.285ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 6.481m | 6.711m | 739.782us | 3 | 4 | 75.00 | ||
| chip_rv_dm_lc_disabled | 8.593m | 8.814m | 1.037ms | 3 | 5 | 60.00 | ||
| chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | |||||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 2.818m | 3.588m | 172.857us | 1 | 1 | 100.00 |
| chip_sw_aes_enc_jitter_en | 2.875m | 3.574m | 172.902us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 2.488m | 3.055m | 164.153us | 1 | 1 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 2.665m | 3.282m | 165.041us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | |||
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 2.804m | 3.367m | 173.592us | 4 | 4 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 2.740m | 3.429m | 173.685us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 2.718m | 3.629m | 177.854us | 1 | 1 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 2.648m | 4.059m | 166.686us | 1 | 1 | 100.00 |
| chip_sw_kmac_mode_kmac | 3.116m | 4.125m | 188.494us | 1 | 1 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 3.106m | 4.307m | 188.566us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 4.562m | 5.478m | 304.513us | 0 | 1 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 45.397s | 45.397s | 0 | 1 | 0.00 | |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 3.587m | 6.478m | 226.742us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 2.472m | 3.352m | 163.320us | 1 | 1 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 5.079m | 5.725m | 269.979us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 5.079m | 5.725m | 269.979us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 0 | 0 | -- | |||
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 2.625m | 3.108m | 167.301us | 1 | 1 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 46.229m | 46.827m | 1.914ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 0 | 0 | -- | |||||
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 4.562m | 5.478m | 304.513us | 0 | 1 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 4.278m | 5.219m | 304.389us | 0 | 1 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 0 | 0 | -- | |||
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | |||
| V2 | chip_sw_keymgr_sideload_acc | chip_sw_keymgr_sideload_acc | 0 | 0 | -- | |||
| V2 | chip_sw_acc_op | chip_sw_acc_ecdsa_op_irq | 51.409m | 52.021m | 1.464ms | 1 | 1 | 100.00 |
| chip_sw_acc_ecdsa_op_irq_jitter_en | 52.360m | 53.027m | 1.464ms | 1 | 1 | 100.00 | ||
| V2 | chip_sw_acc_rnd_entropy | chip_sw_acc_randomness | 3.916m | 4.413m | 244.560us | 1 | 1 | 100.00 |
| V2 | chip_sw_acc_urnd_entropy | chip_sw_acc_randomness | 3.916m | 4.413m | 244.560us | 1 | 1 | 100.00 |
| V2 | chip_sw_acc_idle | chip_sw_acc_randomness | 3.916m | 4.413m | 244.560us | 1 | 1 | 100.00 |
| V2 | chip_sw_acc_mem_scramble | chip_sw_acc_mem_scramble | 5.169m | 5.809m | 278.351us | 1 | 1 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 13.194m | 13.940m | 1.285ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 13.194m | 13.940m | 1.285ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 6.018m | 6.734m | 348.879us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | |||||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 0 | 0 | -- | |||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | |||
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 16.608m | 19.524m | 951.284us | 87 | 100 | 87.00 |
| chip_sw_data_integrity_escalation | 0 | 0 | -- | |||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_acc_mem_scramble | 5.169m | 5.809m | 278.351us | 1 | 1 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 4.562m | 5.478m | 304.513us | 0 | 1 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 6.018m | 6.734m | 348.879us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 2.719m | 3.316m | 180.034us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_acc_mem_scramble | 5.169m | 5.809m | 278.351us | 1 | 1 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 4.562m | 5.478m | 304.513us | 0 | 1 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 6.018m | 6.734m | 348.879us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 2.719m | 3.316m | 180.034us | 1 | 1 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 0 | 0 | -- | |||
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 2.401m | 6.072m | 168.097us | 1 | 1 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_lc_ctrl_transition | 13.218m | 13.656m | 1.016ms | 15 | 15 | 100.00 |
| chip_prim_tl_access | 6.481m | 6.711m | 739.782us | 3 | 4 | 75.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | |||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | |||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 6.481m | 6.711m | 739.782us | 3 | 4 | 75.00 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 0 | 0 | -- | |||
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 0 | 0 | -- | |||
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 0 | 0 | -- | |||
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 0 | -- | |||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 52.360m | 53.027m | 1.464ms | 1 | 1 | 100.00 |
| chip_sw_aes_enc_jitter_en | 2.875m | 3.574m | 172.902us | 1 | 1 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 2.740m | 3.429m | 173.685us | 1 | 1 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 4.278m | 5.219m | 304.389us | 0 | 1 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 3.106m | 4.307m | 188.566us | 1 | 1 | 100.00 | ||
| chip_sw_clkmgr_jitter | 2.504m | 3.218m | 161.186us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | |||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | |||||
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 0 | 0 | -- | |||
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | |||
| chip_sw_sensor_ctrl_alert | 0 | 0 | -- | |||||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 0 | 0 | -- | |||
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | |||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 2.403m | 5.100m | 156.320us | 0 | 1 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 2.403m | 5.100m | 156.320us | 0 | 1 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 2.228m | 3.744m | 157.555us | 0 | 1 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 2.733m | 4.495m | 183.191us | 0 | 1 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 4.867m | 5.523m | 269.052us | 0 | 1 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 2.800m | 3.416m | 173.352us | 0 | 1 | 0.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 3.039m | 3.657m | 179.845us | 4 | 4 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 2.719m | 3.316m | 180.034us | 1 | 1 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 5.957m | 8.844m | 412.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 5.957m | 8.844m | 412.000us | 0 | 1 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 2.749m | 3.602m | 172.910us | 1 | 1 | 100.00 |
| chip_sw_aon_timer_smoketest | 2.955m | 3.685m | 181.483us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 2.588m | 3.534m | 162.213us | 1 | 1 | 100.00 | ||
| chip_sw_csrng_smoketest | 2.606m | 3.133m | 163.762us | 1 | 1 | 100.00 | ||
| chip_sw_gpio_smoketest | 2.767m | 3.502m | 192.946us | 1 | 1 | 100.00 | ||
| chip_sw_hmac_smoketest | 3.126m | 3.856m | 194.116us | 1 | 1 | 100.00 | ||
| chip_sw_kmac_smoketest | 3.038m | 3.755m | 185.477us | 1 | 1 | 100.00 | ||
| chip_sw_acc_smoketest | 3.682m | 4.108m | 223.668us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 2.644m | 3.067m | 166.002us | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 2.778m | 3.405m | 163.965us | 1 | 1 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 3.626m | 4.208m | 266.253us | 1 | 1 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 2.469m | 3.068m | 160.896us | 1 | 1 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 2.605m | 3.003m | 163.982us | 1 | 1 | 100.00 | ||
| chip_sw_uart_smoketest | 2.950m | 3.476m | 174.921us | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 0 | 0 | -- | |||||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 0 | 0 | -- | |||
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 0 | 0 | -- | |||
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | |||
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 11.105s | 11.105s | 0 | 1 | 0.00 | |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 2.535m | 5.826m | 220.249us | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.533m | 6.392m | 220.889us | 4 | 4 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.512m | 7.195m | 232.390us | 4 | 4 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.111m | 6.066m | 218.833us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.152m | 38.832m | 2.983ms | 1 | 1 | 100.00 |
| chip_rv_dm_lc_disabled | 8.593m | 8.814m | 1.037ms | 3 | 5 | 60.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 14.949m | 18.673m | 1.070ms | 1 | 1 | 100.00 |
| chip_sw_lc_walkthrough_prod | 14.786m | 19.541m | 1.071ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 12.064m | 16.625m | 882.353us | 1 | 1 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 12.786m | 15.534m | 882.174us | 1 | 1 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 35.152m | 38.832m | 2.983ms | 1 | 1 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 1.758h | 1.837h | 10.570ms | 0 | 1 | 0.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 1.559h | 1.611h | 10.321ms | 0 | 1 | 0.00 | ||
| rom_volatile_raw_unlock | 0 | 0 | -- | |||||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 0 | -- | |||
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 0 | -- | |||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 0 | 0 | -- | |||
| V2 | tl_d_oob_addr_access | chip_tl_errors | 2.130s | 15.823s | 0 | 30 | 0.00 | |
| V2 | tl_d_illegal_access | chip_tl_errors | 2.130s | 15.823s | 0 | 30 | 0.00 | |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 1.907h | 1.951h | 12.027ms | 0 | 1 | 0.00 |
| chip_same_csr_outstanding | 2.063h | 2.063h | 0 | 1 | 0.00 | |||
| chip_csr_hw_reset | 0 | 0 | -- | |||||
| chip_csr_rw | 0 | 0 | -- | |||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 1.907h | 1.951h | 12.027ms | 0 | 1 | 0.00 |
| chip_same_csr_outstanding | 2.063h | 2.063h | 0 | 1 | 0.00 | |||
| chip_csr_hw_reset | 0 | 0 | -- | |||||
| chip_csr_rw | 0 | 0 | -- | |||||
| V2 | xbar_base_random_sequence | xbar_random | 3.094m | 3.320m | 488.458us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 8.520s | 22.138s | 14.271us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 5.557m | 5.777m | 2.796ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 6.726m | 6.949m | 2.489ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.411m | 1.642m | 75.152us | 4 | 4 | 100.00 | ||
| xbar_random_large_delays | 21.287m | 21.510m | 11.294ms | 3 | 3 | 100.00 | ||
| xbar_random_slow_rsp | 34.454m | 34.669m | 12.883ms | 3 | 3 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.686m | 1.906m | 215.575us | 3 | 3 | 100.00 |
| xbar_error_and_unmapped_addr | 1.888m | 2.116m | 247.115us | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 2.858m | 3.093m | 418.578us | 5 | 5 | 100.00 |
| xbar_error_and_unmapped_addr | 1.888m | 2.116m | 247.115us | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 5.473m | 5.698m | 834.133us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 55.790m | 56.020m | 20.955ms | 5 | 5 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 2.632m | 2.846m | 499.293us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 14.111m | 14.325m | 2.368ms | 5 | 5 | 100.00 |
| xbar_stress_all_with_error | 24.447m | 24.663m | 4.044ms | 15 | 15 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 36.333m | 36.552m | 5.249ms | 24 | 24 | 100.00 |
| xbar_stress_all_with_reset_error | 40.075m | 40.305m | 5.806ms | 25 | 25 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 0 | 0 | -- | |||
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 0 | -- | |||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 0 | 0 | -- | |||
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 0 | -- | |||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 0 | -- | |||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0 | 0 | -- | |||||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0 | 0 | -- | |||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_asm_init_dev | 0 | 0 | -- | |||||
| rom_e2e_asm_init_prod | 0 | 0 | -- | |||||
| rom_e2e_asm_init_prod_end | 0 | 0 | -- | |||||
| rom_e2e_asm_init_rma | 0 | 0 | -- | |||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 0 | -- | |||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 0 | -- | |||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 0 | -- | |||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 0 | 0 | -- | |||
| V2 | TOTAL | 1030 | 1116 | 92.29 | ||||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 3.407m | 3.938m | 193.246us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 2.290m | 3.085m | 130.232us | 5 | 5 | 100.00 |
| V2S | TOTAL | 8 | 8 | 100.00 | ||||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | |||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | |||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | |||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | |||||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 0 | 0 | -- | |||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 16.608m | 19.524m | 951.284us | 87 | 100 | 87.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | |||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | |||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | |||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | |||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 0 | -- | |||
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 2.744m | 7.092m | 176.180us | 0 | 1 | 0.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | |||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 0 | -- | |||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 0 | -- | |||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | |||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | |||||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 0 | 0 | -- | |||
| rom_e2e_jtag_inject_dev | 0 | 0 | -- | |||||
| rom_e2e_jtag_inject_rma | 0 | 0 | -- | |||||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | |||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | |||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 1 | 0.00 | ||||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 15.034m | 18.267m | 951.221us | 1 | 1 | 100.00 | |
| chip_sw_entropy_src_kat_test | 2.553m | 3.075m | 163.210us | 1 | 1 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 2.509m | 2.911m | 160.963us | 1 | 1 | 100.00 | ||
| chip_sw_dma_inline_hashing | 3.226m | 4.496m | 207.560us | 4 | 4 | 100.00 | ||
| chip_sw_dma_abort | 2.909m | 4.107m | 185.300us | 0 | 1 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 3.548m | 3.972m | 202.054us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 6.521m | 7.017m | 431.647us | 7 | 7 | 100.00 | ||
| TOTAL | 1160 | 1251 | 92.73 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 7 | 7 | 6 | 85.71 |
| V1 | 15 | 7 | 4 | 26.67 |
| V2 | 220 | 115 | 84 | 38.18 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 21 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 68.90 | 66.68 | 71.03 | 64.00 | 37.50 | 77.16 | 77.03 | 88.92 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory. has 30 failures:
0.chip_tl_errors.92864360306289758038579713378302294982720044946339046758649305521378645512937
Line 220, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.chip_tl_errors.59131881081666776597747240627393141851252438196555055528599954111135501693634
Line 220, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/1.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 28 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.32766524135381990857037504459736049699875286339544789301723427182895546986053
Line 287, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.6379283230982576742333459873520382688088474428786831018512405522086331306066
Line 287, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
UVM_ERROR @ * us: (chip_sw_spi_passthrough_vseq.sv:101) [chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == * (* [*] vs * [*]) has 5 failures:
0.chip_sw_spi_device_pass_through.92621762513365217284288424537924094134485803108677571685060081269281181945116
Line 371, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
UVM_ERROR @ 465.559505 us: (chip_sw_spi_passthrough_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 465.559505 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_spi_device_pass_through.13849946667227820929782484026261983651112886095491286412455960892562694307402
Line 371, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_spi_device_pass_through/latest/run.log
UVM_ERROR @ 422.018501 us: (chip_sw_spi_passthrough_vseq.sv:101) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 422.018501 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 5 failures:
Test chip_sw_rstmgr_cpu_info has 1 failures.
0.chip_sw_rstmgr_cpu_info.37333401455514558484628075023644035589312360304494215878629380679966713686188
Line 390, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 412.000000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_aes_trans has 1 failures.
0.chip_sw_clkmgr_off_aes_trans.65614581972102701073870603670901241204854454655592230869623077666275730935475
Line 364, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.688000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.688000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_hmac_trans has 1 failures.
0.chip_sw_clkmgr_off_hmac_trans.51229797928345641516188651633144879722164683588842561332017456248176583644012
Line 364, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.640000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_kmac_trans has 1 failures.
0.chip_sw_clkmgr_off_kmac_trans.20387369929184853218264190489829213776556494204827750896610491132058100082220
Line 364, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.608000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.608000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_clkmgr_off_acc_trans has 1 failures.
0.chip_sw_clkmgr_off_acc_trans.80585708994543698866713905870765153867510705776663334880895822628583206385226
Line 364, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_acc_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.688000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.688000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 4 failures:
Test chip_sw_otp_ctrl_escalation has 1 failures.
0.chip_sw_otp_ctrl_escalation.115131647733985180411605707364692296813641976150707244528689658633482364138581
Line 369, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.180000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.180000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_all_escalation_resets has 3 failures.
23.chip_sw_all_escalation_resets.74093304134650659447535338200685729314719246480248617535396766695226655235391
Line 370, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.092000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.092000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.chip_sw_all_escalation_resets.11142429472948433805761168133780913912924988386733541977381391932403930149148
Line 370, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/44.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.028000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.028000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 4 failures:
Test chip_sw_keymgr_dpe_key_derivation has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation.86732344185064046099130809786208952360740107334874535734254502678765947888433
Line 384, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 304.513000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (6940877641445576684307115537121822166069297037100409927284249702812096590656014149017696769705252334726695817554832708402605433817518739317728573552680028 [0x84864d9eaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd302d0fd6f7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.513000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.6330321227369516874731968818716428992579296458309195883205425753141303997505
Line 384, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 304.506000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (13076468512800777672872047424890207842354972120472116828130754338681021773037171014171396791563339923905860786405021301089054705658690688545736580506410076 [0xf9ac7258aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd37ffac2a97f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.506000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.26775368318471702428348516259227302151784667742276593721089562887675456853970
Line 384, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_ERROR @ 304.389000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (656507768001674463697742649349558309515901873662387998135140418813104487123633749277978403567989473473444525702662526180180602343575491799674974701444188 [0xc88f170aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd38ade41817f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.389000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq has 1 failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.115140092254358738766811888556154453264866092869074000737177613788979350032884
Line 384, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log
UVM_ERROR @ 3916.649760 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4444493697255233379856221067454681028802248920967604102042924201335158206079444609430197199957856782779970532039708701805729663892090358163952065795415132 [0x54dc3b8faae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3d28a8b7e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 3916.649760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 4 failures:
21.chip_sw_all_escalation_resets.15415906907803522458454887530666284917281964944255065855472492604760557444772
Line 351, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/21.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.160001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.chip_sw_all_escalation_resets.54542989289948350886372294874006186237209163992030055045068177343398899101350
Line 351, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/43.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.260001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job returned non-zero exit code has 3 failures:
Test chip_sw_example_manufacturer has 1 failures.
0.chip_sw_example_manufacturer.93375259258837939185272486952857103873170171877654944398256029302878214848981
Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (246fe9) <-- target platform (//toolchain:pavona_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 12.814s, Critical Path: 0.20s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nfshome/luism/claude-dv-home/pavona/pavona-work/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Test chip_sw_kmac_app_rom has 1 failures.
0.chip_sw_kmac_app_rom.110572462315935751324613802764017998300521274453956550426031747827930845247924
Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
---- STDERR ----
WARNING: Output base '/nfshome/luism/.cache/bazel/_bazel_luism/c44fc6b1221d566af8bd7ea3631efcfb' is on NFS. This may lead to surprising failures and undetermined behavior.
Another command (pid=1060061) is running. Waiting for it to complete on the server (server_pid=649715)...
Another command (pid=1058745) is running. Waiting for it to complete on the server (server_pid=649715)...
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nfshome/luism/claude-dv-home/pavona/pavona-work/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Test base_rom_e2e_smoke has 1 failures.
0.base_rom_e2e_smoke.4673275418610228156610871456046722777012103775774932141075434679203933193035
Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.base_rom_e2e_smoke/latest/run.log
_deploy_software_collateral(args)
File "/nfshome/luism/claude-dv-home/pavona/pavona-work/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
^^^^^^^^^^^^^^^^^^
File "<string>", line 4, in __init__
File "/nfshome/luism/claude-dv-home/pavona/pavona-work/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
^^^^^^^^^^^^^^^^^^^
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/nfshome/luism/claude-dv-home/pavona/pavona-work/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 3 failures:
3.chip_sw_all_escalation_resets.11638336130359252063567052964523803858418722895820515427218031620460401708524
Line 369, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 178.144000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 178.144000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
85.chip_sw_all_escalation_resets.105329867454430989569679216445575475803418986837744444572213208209654398175683
Line 369, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/85.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 178.248000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 178.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
37.chip_sw_all_escalation_resets.28119200425543570922769746892370518543580851487109433088563822164623197543544
Line 370, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 176.800000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 176.800000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
51.chip_sw_all_escalation_resets.110118342226591768376932542284906549608934684246354430784105155177943806047988
Line 370, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/51.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 176.798000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 176.798000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:433) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = * ns has 2 failures:
Test chip_csr_bit_bash has 1 failures.
0.chip_csr_bit_bash.48234257740104243235144178912819211009900007765649487901646522382249422491716
Line 313, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_bit_bash/latest/run.log
UVM_ERROR @ 12018.562269 us: (chip_sw_base_vseq.sv:433) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns
UVM_INFO @ 12018.562269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_csr_aliasing has 1 failures.
0.chip_csr_aliasing.108014606777136916172936072678210281235952555115204921812598463628210148270598
Line 313, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_aliasing/latest/run.log
UVM_ERROR @ 12026.943256 us: (chip_sw_base_vseq.sv:433) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInBootRom, TIMEOUT = 12000000 ns
UVM_INFO @ 12026.943256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_lc_volatile_raw_unlock_vseq.sv:52) [chip_sw_lc_volatile_raw_unlock_vseq] wait timeout occurred! has 2 failures:
Test chip_sw_lc_ctrl_volatile_raw_unlock has 1 failures.
0.chip_sw_lc_ctrl_volatile_raw_unlock.101641295689119993976455764567666007050677746174346441689391478424962342735474
Line 368, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log
UVM_FATAL @ 10569.949433 us: (chip_sw_lc_volatile_raw_unlock_vseq.sv:52) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] wait timeout occurred!
UVM_INFO @ 10569.949433 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz has 1 failures.
0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.103644447832374762580597901705265847016337710164961652931924142715537986700187
Line 371, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest/run.log
UVM_FATAL @ 10320.761700 us: (chip_sw_lc_volatile_raw_unlock_vseq.sv:52) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_volatile_raw_unlock_vseq] wait timeout occurred!
UVM_INFO @ 10320.761700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:
Test chip_jtag_csr_rw has 1 failures.
0.chip_jtag_csr_rw.100978651224378576670992029397465522186324841293173914608205313895791675286372
Line 5980, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.027000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hf6cfe586 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h0 a_user: 'h26940 a_blocked: 'h0 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.027000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_jtag_mem_access has 1 failures.
0.chip_jtag_mem_access.29135103235376995115521815857653365194964544938992482142705308222610088915529
Line 5980, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.032000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'h5de1bb77 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h1 a_user: 'h248d5 a_blocked: 'h0 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.032000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:73) [chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == * (* [*] vs * [*]) Writes to dmcontrol must be gated in this LC state has 2 failures:
2.chip_rv_dm_lc_disabled.60154665955711172285220636194157980461258351765685267226719330646929080871285
Line 210, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 124.883766 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 124.883766 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.chip_rv_dm_lc_disabled.112751268247144912201996816366141775048713896208378620792786314592264935397416
Line 210, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/3.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 123.721647 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 123.721647 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after running for * minutes has 1 failures:
0.chip_same_csr_outstanding.55255245600486552546975652684272255030708966892066452820440574474461549470175
Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
Job timed out after running for 120 minutes
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:172) [chip_sw_spi_passthrough_collision_vseq] Check failed host_rsp_q.size() == device_rsp_q.size() (* [*] vs * [*]) has 1 failures:
0.chip_sw_spi_device_pass_through_collision.15903377274404963866790374094172374853521772738960237223813104995067932751567
Line 373, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 204.354501 us: (chip_sw_spi_passthrough_collision_vseq.sv:172) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Check failed host_rsp_q.size() == device_rsp_q.size() (1 [0x1] vs 0 [0x0])
UVM_INFO @ 204.354501 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
0.chip_sw_rstmgr_alert_info.106053297565066326777021468736847530754943464278857686468490809032087585053725
Line 542, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 343.981000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3 obs:0x1
UVM_INFO @ 343.981000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 1 failures:
0.chip_sw_soc_proxy_smoketest.8159654826299313551496275097867159779655870168365781009612006734669322422458
Line 362, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
UVM_ERROR @ 156.320000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 156.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
0.chip_sw_soc_proxy_external_wakeup.32074377824613724341553758265758995474211623146972070807177411052527149834513
Line 360, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 157.555000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.555000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
0.chip_sw_soc_proxy_gpios.60734738635693009090883668335266459132854683588397796112589658538785467156152
Line 361, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 183.191000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=410009fc MTVAL=00000004
UVM_INFO @ 183.191000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 1 failures:
0.chip_sw_aon_timer_irq.46899868356543968189316572007312002087285652132876345871668518317343366421863
Line 361, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 555.585000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 3991 usec which is not in the range 364 usec and 417 usec
UVM_INFO @ 555.585000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
0.chip_sw_aon_timer_wdog_bite_reset.19960416194881771989563068278720779983043865185829423283689963826012502364042
Line 362, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 182.141000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 182.141000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
0.chip_sw_rv_core_ibex_rnd.49176687291699371243570388141530902795956610465130487614305982117098057813258
Line 360, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
UVM_ERROR @ 173.352000 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
UVM_INFO @ 173.352000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
0.chip_sw_rv_core_ibex_nmi_irq.74809127479904431592994445380721570819154775521054162634460146771281512722201
Line 363, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 269.052000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 269.052000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
0.chip_sw_dma_abort.68817570266207084770527125395836096482037112163511514361952305105691055186486
Line 368, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_FATAL @ 185.300000 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
UVM_INFO @ 185.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:653) [chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 1 failures:
1.chip_prim_tl_access.32660828570527814718452252920302682407704080309023012039312036519939686264427
Line 234, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_dragonfly-sim-vcs/1.chip_prim_tl_access/latest/run.log
UVM_ERROR @ 117.725000 us: (cip_base_vseq.sv:653) [uvm_test_top.env.virtual_sequencer.chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x30140004
UVM_INFO @ 117.725000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---