CHIP_EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: `2aab100d17`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
	crypto_lib_hash_stress	crypto_lib_hash_stress				0	0	--
	crypto_lib_ecc_stress	crypto_lib_ecc_stress				0	0	--
	crypto_lib_rsa_key_gen_stress	crypto_lib_rsa_key_gen_stress				0	0	--
	crypto_lib_rsa_stress	crypto_lib_rsa_stress				0	0	--
	crypto_lib_aes_stress	crypto_lib_aes_stress				0	0	--
	crypto_lib_symmetric_keygen	crypto_lib_symmetric_keygen				0	0	--
	crypto_lib_entropy	crypto_lib_entropy				0	0	--
V1	chip_sw_example_tests	chip_sw_example_flash	1.795m	14.423m	2.733ms	1	1	100.00
		chip_sw_example_rom	1.076m	8.254m	2.489ms	1	1	100.00
		chip_sw_example_manufacturer	1.966m	11.607m	2.996ms	1	1	100.00
		chip_sw_example_concurrency	2.053m	16.291m	2.960ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset				0	0	--
V1	csr_rw	chip_csr_rw				0	0	--
V1	csr_bit_bash	chip_csr_bit_bash	4.320s	9.746s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	4.360s	9.732s		0	1	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset				0	0	--
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	4.360s	9.732s		0	1	0.00
		chip_csr_rw				0	0	--
V1	xbar_smoke	xbar_smoke	5.950s	18.443s	250.582us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.045m	7.830m	4.158ms	6	6	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.045m	7.830m	4.158ms	6	6	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.045m	7.830m	4.158ms	6	6	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.051m	17.377m	4.046ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.051m	17.377m	4.046ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	4.999m	15.510m	4.052ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	5.375m	20.654m	5.012ms	3	3	100.00
		chip_sw_uart_tx_rx_idx3	5.185m	19.882m	4.408ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	23.066m	27.194m	12.979ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	23.319m	36.012m	13.808ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	14.781m	16.057m	13.242ms	4	4	100.00
V1		TOTAL				157	159	98.74
V2	chip_pin_mux	chip_padctrl_attributes	2.816m	3.039m	4.622ms	4	4	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	2.816m	3.039m	4.622ms	4	4	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.429m	15.177m	3.798ms	5	5	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.559m	15.816m	5.444ms	5	5	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.828m	15.798m	3.883ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	7.115m	8.696m	8.986ms	3	3	100.00
		chip_tap_straps_testunlock0	4.018m	4.332m	5.637ms	3	3	100.00
		chip_tap_straps_rma	2.955m	4.160m	5.080ms	5	5	100.00
		chip_tap_straps_prod	10.637m	10.969m	12.460ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.747m	15.982m	3.610ms	4	4	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	9.152m	24.247m	9.680ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.751m	15.195m	5.705ms	5	5	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.751m	15.195m	5.705ms	5	5	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	8.793m	11.650m	8.581ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	21.727m	22.568m	14.318ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.513m	8.835m	4.326ms	4	4	100.00
		chip_sw_flash_ctrl_access_jitter_en	6.871m	9.238m	5.709ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	47.050m	51.566m	18.563ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.099m	5.985m	2.527ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	1.616m	4.695m	3.120ms	0	1	0.00
		chip_sw_hmac_enc_jitter_en	2.251m	4.563m	2.596ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	2.356m	3.186m	2.672ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	2.553m	6.651m	3.292ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.673m	8.101m	4.213ms	3	3	100.00
		chip_sw_clkmgr_jitter	1.950m	4.591m	2.745ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.034m	3.959m	3.458ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	7.385m	10.309m	7.132ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.220m	4.913m	5.237ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.554m	4.003m	3.565ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.220m	4.913m	5.237ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.087m	3.338m	2.982ms	1	1	100.00
		chip_sw_aes_smoketest	2.725m	5.257m	3.451ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.840m	5.391m	3.064ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.540m	4.939m	3.317ms	1	1	100.00
		chip_sw_csrng_smoketest	1.890m	4.724m	2.967ms	1	1	100.00
		chip_sw_entropy_src_smoketest	12.292m	15.577m	7.622ms	1	1	100.00
		chip_sw_gpio_smoketest	2.977m	6.028m	3.235ms	1	1	100.00
		chip_sw_hmac_smoketest	2.839m	4.973m	3.364ms	1	1	100.00
		chip_sw_kmac_smoketest	2.927m	5.004m	2.689ms	1	1	100.00
		chip_sw_acc_smoketest	12.000m	13.449m	7.763ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.024m	5.157m	5.166ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.161m	6.475m	5.456ms	1	1	100.00
		chip_sw_rv_plic_smoketest	1.788m	4.033m	2.498ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.722m	3.114m	3.172ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.324m	4.218m	3.372ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.764m	3.866m	2.522ms	1	1	100.00
		chip_sw_uart_smoketest	2.217m	4.133m	2.823ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	1.929m	4.618m	3.075ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	2.003m	3.600m	2.832ms	0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.073h	2.224h	59.941ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.162m	41.482m	15.109ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	8.613m	10.249m	14.832ms	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.756m	3.673m	3.591ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.758m	3.590m	3.992ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.598h	1.835h	51.909ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.822m	14.542m	3.237ms	0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.290s	16.381s		0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.290s	16.381s		0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	4.360s	9.732s		0	1	0.00
		chip_same_csr_outstanding	4.250s	8.682s		0	1	0.00
		chip_csr_hw_reset				0	0	--
		chip_csr_rw				0	0	--
V2	tl_d_partial_access	chip_csr_aliasing	4.360s	9.732s		0	1	0.00
		chip_same_csr_outstanding	4.250s	8.682s		0	1	0.00
		chip_csr_hw_reset				0	0	--
		chip_csr_rw				0	0	--
V2	xbar_base_random_sequence	xbar_random	53.680s	1.088m	2.714ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.350s	16.704s	52.718us	100	100	100.00
		xbar_smoke_large_delays	1.017m	1.219m	11.259ms	100	100	100.00
		xbar_smoke_slow_rsp	54.500s	1.107m	6.756ms	100	100	100.00
		xbar_random_zero_delays	32.870s	45.379s	596.967us	100	100	100.00
		xbar_random_large_delays	4.675m	4.870m	50.582ms	3	3	100.00
		xbar_random_slow_rsp	3.323m	3.529m	24.873ms	3	3	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	27.200s	39.540s	1.104ms	3	3	100.00
		xbar_error_and_unmapped_addr	14.540s	26.174s	252.273us	4	4	100.00
V2	xbar_error_cases	xbar_error_random	46.250s	57.943s	2.467ms	100	100	100.00
		xbar_error_and_unmapped_addr	14.540s	26.174s	252.273us	4	4	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.115m	1.308m	2.982ms	9	9	100.00
		xbar_access_same_device_slow_rsp	11.321m	11.519m	86.974ms	13	13	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	42.640s	54.500s	2.639ms	4	4	100.00
V2	xbar_stress_all	xbar_stress_all	3.786m	3.986m	11.582ms	15	15	100.00
		xbar_stress_all_with_error	4.755m	4.955m	14.629ms	6	6	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	8.053m	8.266m	16.364ms	20	20	100.00
		xbar_stress_all_with_reset_error	9.914m	10.120m	11.059ms	8	8	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.162m	41.482m	15.109ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	32.386m	33.471m	27.307ms	2	3	66.67
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.068m	41.685m	16.706ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.443m	32.196m	11.553ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	41.461m	43.373m	15.971ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.280m	41.028m	15.468ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.710m	42.317m	100.019ms	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.071m	40.224m	15.113ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	14.940s	1.773m	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.140s	1.958m	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	15.180s	1.673m	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	15.130s	1.725m	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	15.240s	1.726m	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	15.240s	2.183m	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	15.080s	2.302m	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	15.200s	2.470m	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	15.190s	2.437m	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.300s	2.287m	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	15.220s	3.190m	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	15.020s	3.110m	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	15.150s	2.735m	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	15.040s	2.876m	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	15.140s	3.167m	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	15.190s	2.576m	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	15.120s	2.186m	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	15.040s	2.122m	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	14.940s	2.024m	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	15.190s	3.822m	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.310s	3.063m	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.000s	3.350m	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	15.040s	3.857m	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.990s	2.792m	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	15.140s	3.399m	10.300us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.095m	34.914m	11.632ms	1	1	100.00
		rom_e2e_asm_init_dev	42.159m	45.217m	15.187ms	1	1	100.00
		rom_e2e_asm_init_prod	4.181m	6.629m	10.010ms	0	1	0.00
		rom_e2e_asm_init_prod_end	43.532m	43.963m	16.716ms	2	3	66.67
		rom_e2e_asm_init_rma	40.264m	42.929m	15.276ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	41.965m	43.365m	17.815ms	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	41.264m	42.827m	17.708ms	0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.356m	39.220m	15.436ms	0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.014m	41.486m	16.256ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	39.069m	46.367m	34.528ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	39.069m	46.367m	34.528ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.020m	6.829m	2.915ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.099m	5.985m	2.527ms	1	1	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block				0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption				0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.705m	3.342m	2.973ms	1	1	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed				0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed				0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.526m	7.531m	2.737ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	2.426m	4.554m	2.811ms	0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.110m	5.265m	2.856ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	5.205m	9.946m	5.477ms	1	1	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset				0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods				0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	4.981m	5.695m	3.959ms	6	6	100.00
		chip_plic_all_irqs_10	5.534m	6.025m	4.220ms	7	7	100.00
		chip_plic_all_irqs_20	5.276m	5.982m	4.396ms	7	7	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	2.703m	4.264m	3.606ms	4	4	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	15.641m	19.246m	11.127ms	5	5	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.145m	6.729m	3.750ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.605m	4.582m	3.384ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	4.045h	4.045h		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.303m	13.831m	7.099ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	8.759m	10.357m	6.394ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	9.795m	12.909m	7.684ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.042h	2.096h	255.082ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.207m	4.008m	4.541ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.024m	5.157m	5.166ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.207m	4.008m	4.541ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.502m	10.456m	7.811ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.502m	10.456m	7.811ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.993m	6.030m	8.096ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.324m	6.808m	4.941ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_acc_randomness	7.978m	15.429m	6.480ms	1	1	100.00
		chip_sw_aes_idle	2.526m	7.531m	2.737ms	3	3	100.00
		chip_sw_hmac_enc_idle	2.382m	3.997m	3.092ms	1	1	100.00
		chip_sw_kmac_idle	2.245m	5.955m	2.986ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.697m	6.706m	4.095ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.937m	6.740m	3.724ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.187m	6.319m	3.991ms	1	1	100.00
		chip_sw_clkmgr_off_acc_trans	3.508m	6.568m	4.553ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	10.183m	11.065m	9.790ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	4.885m	7.859m	4.784ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.986m	8.428m	4.412ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.550m	7.175m	4.018ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.489m	6.017m	4.705ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.513m	7.174m	3.807ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.561m	6.639m	4.691ms	1	1	100.00
		chip_sw_ast_clk_outputs	8.793m	11.650m	8.581ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	9.438m	12.858m	12.772ms	4	4	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.550m	7.175m	4.018ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.489m	6.017m	4.705ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	4.513m	8.835m	4.326ms	4	4	100.00
		chip_sw_flash_ctrl_access_jitter_en	6.871m	9.238m	5.709ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	47.050m	51.566m	18.563ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.099m	5.985m	2.527ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	1.616m	4.695m	3.120ms	0	1	0.00
		chip_sw_hmac_enc_jitter_en	2.251m	4.563m	2.596ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	2.356m	3.186m	2.672ms	0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	2.553m	6.651m	3.292ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.673m	8.101m	4.213ms	3	3	100.00
		chip_sw_clkmgr_jitter	1.950m	4.591m	2.745ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.933m	2.818m	3.335ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	4.433m	5.570m	4.257ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	7.487m	8.618m	7.094ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq	54.296m	54.861m	24.159ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.885m	3.083m	2.915ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.038m	3.086m	3.149ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1.398m	2.499m	2.918ms	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.718m	3.792m	3.702ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	4.400m	5.649m	4.435ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.095m	18.578m	22.620ms	5	5	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	2.421h	2.429h	95.554ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	8.793m	11.650m	8.581ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	4.996m	8.566m	4.782ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.661m	6.134m	3.625ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	10.303m	13.831m	7.099ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	14.408m	14.957m	6.853ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.091m	5.715m	2.787ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	2.462m	7.383m	2.931ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.370m	6.240m	3.442ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.934h	2.018h	45.935ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	2.047m	4.067m	2.511ms	1	1	100.00
		chip_sw_edn_entropy_reqs	1.822m	3.938m	2.599ms	0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.047m	4.067m	2.511ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	14.408m	14.957m	6.853ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test				0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.091m	4.828m	3.025ms	1	1	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous				0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert				0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	19.418m	19.899m	25.820ms	7	7	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	6.494m	9.205m	4.856ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	6.871m	9.238m	5.709ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	4.131m	5.771m	3.570ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	4.513m	8.835m	4.326ms	4	4	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	49.770m	50.096m	42.291ms	7	7	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	19.418m	19.899m	25.820ms	7	7	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	2.587m	6.428m	3.778ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	2.080m	2.523m	2.805ms	0	1	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	1.672m	3.382m	2.750ms	0	1	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	49.770m	50.096m	42.291ms	7	7	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	1.672m	3.382m	2.750ms	0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	1.672m	3.382m	2.750ms	0	1	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	1.672m	3.382m	2.750ms	0	1	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	1.672m	3.382m	2.750ms	0	1	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	1.112m	1.309m	3.939ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	6.236m	9.622m	5.953ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	4.338m	5.268m	6.119ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	4.338m	5.268m	6.119ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.257m	4.109m	2.897ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.251m	4.563m	2.596ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.382m	3.997m	3.092ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	12.455m	13.766m	8.389ms	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	4.821m	5.461m	4.170ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.191m	14.593m	4.674ms	4	4	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.537m	11.811m	4.652ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.397m	10.961m	5.974ms	4	4	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.576m	8.404m	4.222ms	4	4	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	2.080m	2.523m	2.805ms	0	1	0.00
		chip_sw_keymgr_key_derivation_jitter_en	2.356m	3.186m	2.672ms	0	3	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	1.526m	5.460m	3.503ms	0	1	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	2.426m	4.554m	2.811ms	0	3	0.00
V2	chip_sw_keymgr_sideload_acc	chip_sw_keymgr_sideload_acc	2.072m	7.003m	2.394ms	0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.530m	4.670m	3.126ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.405m	6.777m	3.153ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.553m	6.651m	3.292ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	2.080m	2.523m	2.805ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.241m	6.515m	3.023ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	8.854m	11.918m	6.452ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.245m	5.955m	2.986ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	5.205m	9.946m	5.477ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	7.115m	8.696m	8.986ms	3	3	100.00
		chip_tap_straps_rma	2.955m	4.160m	5.080ms	5	5	100.00
		chip_tap_straps_prod	10.637m	10.969m	12.460ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.610m	3.820m	2.637ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	2.162m	2.595m	3.397ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	1.672m	3.382m	2.750ms	0	1	0.00
		chip_sw_flash_rma_unlocked	49.770m	50.096m	42.291ms	7	7	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.952m	4.881m	2.874ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	2.010m	5.053m	3.480ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.881m	4.171m	3.176ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.741m	5.020m	2.911ms	0	1	0.00
		chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
		chip_sw_keymgr_key_derivation	2.080m	2.523m	2.805ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	5.132m	8.622m	9.872ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	1.904m	5.534m	3.105ms	0	1	0.00
		chip_prim_tl_access	1.112m	1.309m	3.939ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	9.438m	12.858m	12.772ms	4	4	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	4.885m	7.859m	4.784ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	4.986m	8.428m	4.412ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.550m	7.175m	4.018ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	4.489m	6.017m	4.705ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	4.513m	7.174m	3.807ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	4.561m	6.639m	4.691ms	1	1	100.00
		chip_tap_straps_dev	7.115m	8.696m	8.986ms	3	3	100.00
		chip_tap_straps_rma	2.955m	4.160m	5.080ms	5	5	100.00
		chip_tap_straps_prod	10.637m	10.969m	12.460ms	5	5	100.00
		chip_rv_dm_lc_disabled	3.325m	3.533m	9.571ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.647m	4.209m	3.602ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.032m	2.801m	3.485ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.260m	4.023m	3.089ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.659m	5.916m	3.740ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	19.424m	26.752m	28.749ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.325m	3.533m	9.571ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	8.318m	16.720m	9.956ms	0	1	0.00
		chip_sw_lc_walkthrough_prod	9.265m	11.837m	9.681ms	0	1	0.00
		chip_sw_lc_walkthrough_prodend	8.403m	12.980m	11.265ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	4.410m	10.191m	4.896ms	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	19.424m	26.752m	28.749ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	45.600s	3.081m	2.469ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	51.010s	8.320m	2.714ms	1	1	100.00
		rom_volatile_raw_unlock	52.320s	2.380m	2.554ms	1	1	100.00
V2	chip_sw_acc_isa	chip_sw_acc_isa				0	0	--
V2	chip_sw_acc_op	chip_sw_acc_ecdsa_op_irq	46.259m	49.363m	17.203ms	1	1	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	47.050m	51.566m	18.563ms	1	1	100.00
V2	chip_sw_acc_rnd_entropy	chip_sw_acc_randomness	7.978m	15.429m	6.480ms	1	1	100.00
V2	chip_sw_acc_urnd_entropy	chip_sw_acc_randomness	7.978m	15.429m	6.480ms	1	1	100.00
V2	chip_sw_acc_idle	chip_sw_acc_randomness	7.978m	15.429m	6.480ms	1	1	100.00
V2	chip_sw_acc_mem_scramble	chip_sw_acc_mem_scramble	3.700m	10.282m	3.626ms	1	1	100.00
V2	chip_sw_acc_keymgr	chip_sw_acc_keymgr				0	0	--
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	19.418m	19.899m	25.820ms	7	7	100.00
		chip_sw_acc_mem_scramble	3.700m	10.282m	3.626ms	1	1	100.00
		chip_sw_keymgr_key_derivation	2.080m	2.523m	2.805ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	4.827m	8.756m	4.488ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.100m	3.673m	2.689ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	19.418m	19.899m	25.820ms	7	7	100.00
		chip_sw_acc_mem_scramble	3.700m	10.282m	3.626ms	1	1	100.00
		chip_sw_keymgr_key_derivation	2.080m	2.523m	2.805ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	4.827m	8.756m	4.488ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.100m	3.673m	2.689ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.597m	6.416m	5.061ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	1.610m	3.820m	2.637ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	1.952m	4.881m	2.874ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	2.010m	5.053m	3.480ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	1.881m	4.171m	3.176ms	0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	1.741m	5.020m	2.911ms	0	1	0.00
		chip_sw_lc_ctrl_transition	9.515m	9.990m	12.894ms	3	3	100.00
		chip_prim_tl_access	1.112m	1.309m	3.939ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	1.112m	1.309m	3.939ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1.668m	3.128m	2.298ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	4.425m	10.454m	10.197ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	18.275m	20.258m	26.960ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.065m	5.211m	7.485ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.028m	9.716m	7.377ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.021m	11.069m	7.429ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	13.210m	14.810m	22.794ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.877m	13.973m	14.416ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.502m	10.456m	7.811ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	9.423m	12.964m	13.180ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	4.592m	7.764m	5.141ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	4.425m	10.454m	10.197ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.179m	6.159m	4.263ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	23.034m	25.942m	29.730ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	3.601m	6.960m	5.803ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.729m	8.120m	6.069ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.588m	24.159m	23.561ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.208m	12.899m	7.514ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.619m	17.097m	11.910ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	25.875m	27.238m	30.323ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.018m	4.128m	3.511ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.132m	8.622m	9.872ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.132m	8.622m	9.872ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.619m	17.097m	11.910ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	20.588m	24.159m	23.561ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	4.592m	7.764m	5.141ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.024m	5.157m	5.166ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.655m	5.450m	4.809ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.328m	10.065m	5.051ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.958m	5.257m	4.896ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	15.641m	19.246m	11.127ms	5	5	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.676m	7.022m	3.225ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	8.759m	10.357m	6.394ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.788m	10.182m	5.445ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.295m	8.574m	4.829ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.671m	3.503m	3.369ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.100m	3.673m	2.689ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.328m	10.065m	5.051ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.328m	10.065m	5.051ms	0	1	0.00
V2	chip_sw_rv_core_ibex_smoke	chip_sw_rv_core_ibex_smoke				0	0	--
V2	chip_sw_rv_core_ibex_epmp_smoke	chip_sw_rv_core_ibex_epmp_smoke				0	0	--
V2	chip_sw_rv_core_ibex_mem_smoke	chip_sw_rv_core_ibex_mem_smoke				0	0	--
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	20.111m	20.315m	16.777ms	7	7	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	11.752m	12.425m	13.674ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.655m	5.450m	4.809ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	2.311m	3.890m	3.382ms	0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	19.595m	20.965m	13.043ms	0	1	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	2.955m	4.160m	5.080ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.325m	3.533m	9.571ms	0	1	0.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag				0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm				0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status				0	0	--
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	4.981m	5.695m	3.959ms	6	6	100.00
		chip_plic_all_irqs_10	5.534m	6.025m	4.220ms	7	7	100.00
		chip_plic_all_irqs_20	5.276m	5.982m	4.396ms	7	7	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.216m	3.198m	3.392ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.304m	4.210m	3.321ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.162m	41.482m	15.109ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	2.276m	6.055m	3.136ms	0	1	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.373m	4.980m	3.472ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.465m	5.960m	2.712ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.778m	4.595m	3.405ms	0	4	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.827m	8.756m	4.488ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.673m	8.101m	4.213ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.099m	8.487m	6.923ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.617m	9.173m	7.656ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	1.904m	5.534m	3.105ms	0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
		chip_sw_data_integrity_escalation	6.751m	15.195m	5.705ms	5	5	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.208m	12.899m	7.514ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	15.213m	15.739m	23.005ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.227m	3.253m	3.347ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.375m	3.786m	3.759ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	4.341m	5.268m	4.793ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	15.213m	15.739m	23.005ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	15.213m	15.739m	23.005ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	30.791m	31.167m	20.131ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	30.791m	31.167m	20.131ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.942m	4.896m	6.077ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	39.069m	46.367m	34.528ms	0	1	0.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem				0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	1.962m	16.382m	2.631ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.545m	16.952m	3.566ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.751m	15.927m	3.724ms	4	4	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof				0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	3.959m	16.564m	4.048ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	12.470m	28.935m	8.579ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.199h	1.336h	31.394ms	4	4	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	21.165m	34.259m	12.180ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.358m	14.312m	3.435ms	1	1	100.00
V2		TOTAL				1114	1321	84.33
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.340m	6.055m	3.146ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.102m	2.666m	3.011ms	4	5	80.00
V2S		TOTAL				5	6	83.33
V3	chip_sw_usb_suspend	chip_sw_usb_suspend				0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.500h	2.527h	67.675ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	5.956m	6.686m	3.966ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.021m	4.110m	3.572ms	0	1	0.00
		rom_e2e_jtag_debug_dev	4.680m	6.289m	6.030ms	0	1	0.00
		rom_e2e_jtag_debug_rma	7.223m	8.151m	14.353ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	58.860s	2.049m	2.649ms	0	1	0.00
		rom_e2e_jtag_inject_dev	52.540s	1.900m	1.963ms	0	1	0.00
		rom_e2e_jtag_inject_rma	47.340s	1.867m	2.192ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma				0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps				0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	10.144s	10.144s		0	1	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw				0	0	--
V3	manuf_scrap	manuf_scrap				0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test				0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution				0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr				0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock				0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token				0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop				0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization				0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization				0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image				0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates				0	0	--
V3	manuf_ft_eom	manuf_ft_eom				0	0	--
V3	manuf_rma_entry	manuf_rma_entry				0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest				0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal				0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot				0	0	--
V3	chip_sw_aes_stall_test	chip_sw_aes_stall_test				0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	2.968m	5.112m	3.292ms	0	1	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	4.243m	8.977m	3.048ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	12.246m	14.094m	6.408ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	8.601m	9.168m	5.842ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.235m	6.218m	2.641ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests				0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests				0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation				0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	7.673m	8.837m	5.149ms	1	1	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress				0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress				0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness				0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe				0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions				0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed				0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override				0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching				0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack				0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart				0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error				0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation				0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing				0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress				0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress				0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress				0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress				0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload				0	0	--
V3	chip_sw_kmac_endianness	chip_sw_kmac_endianness				0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress				0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions				0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error				0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access				0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.521m	2.979m	3.126ms	7	7	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	1.842m	3.482m	2.745ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration				0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked				0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout				0	0	--
V3	chip_sw_pwm_smoketest	chip_sw_pwm_smoketest				0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.797m	6.437m	6.376ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	3.325m	5.506m	4.299ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.619m	17.097m	11.910ms	1	1	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error				0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests				0	0	--
V3	chip_sw_rv_core_ibex_alerts	chip_sw_rv_core_ibex_alerts				0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.021m	4.110m	3.572ms	0	1	0.00
		rom_e2e_jtag_debug_dev	4.680m	6.289m	6.030ms	0	1	0.00
		rom_e2e_jtag_debug_rma	7.223m	8.151m	14.353ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.086m	6.525m	5.930ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.712m	19.719m	5.683ms	71	73	97.26
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.290h	1.312h	37.821ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.290h	1.312h	37.821ms	1	1	100.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model				0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.842m	4.198m	3.381ms	3	3	100.00
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through				0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration				0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events				0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset				0	0	--
V3	chip_sw_sram_readback	chip_sw_sram_readback				0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access				0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity				0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback				0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback				0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break				0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.051m	17.377m	4.046ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	38.197m	51.984m	18.766ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso				0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed				0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume				0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset				0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect				0	0	--
V3		TOTAL				29	41	70.73
	Unmapped tests	chip_sival_flash_info_access	2.713m	15.060m	2.814ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.270m	21.253m	6.077ms	3	3	100.00
		chip_sw_otp_ctrl_rot_auth_config	4.100s	3.402m		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	1.950m	2.978m	2.877ms	0	1	0.00
		chip_sw_otp_ctrl_descrambling	2.567m	3.558m	3.051ms	0	3	0.00
		chip_sw_pwrmgr_lowpower_cancel	3.399m	4.722m	3.651ms	5	5	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.147s	12.147s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.727m	3.504m	3.002ms	1	1	100.00
		chip_egret_csr_hw_reset	2.000s	14.549s		0	5	0.00
		chip_egret_csr_rw	2.050s	14.867s		0	20	0.00
		chip_egret_csr_bit_bash	2.020s	14.253s		0	5	0.00
		chip_egret_csr_aliasing	2.050s	14.421s		0	5	0.00
		chip_egret_same_csr_outstanding	2.070s	14.925s		0	20	0.00
		chip_egret_csr_mem_rw_with_rand_reset	2.070s	14.772s		0	20	0.00
		TOTAL				1317	1620	81.30

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	21	14	4	19.05
V1	18	15	13	72.22
V2	294	275	200	68.03
V2S	2	2	1	50.00
V3	93	23	13	13.98

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.67	94.69	91.32	84.02	37.50	95.44	97.87	98.87

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory. has 105 failures:

Test chip_tl_errors has 30 failures.

0.chip_tl_errors.106760769292106020095413899173236497666958643021489015800492251730412506156703
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_tl_errors.6304105203531370885236628585564628017769566839308315011370802607260783615101
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 28 more failures.

Test chip_egret_csr_hw_reset has 5 failures.

0.chip_egret_csr_hw_reset.17440822505484184053440731536964813056549292601133921425899525489047997387575
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_hw_reset.17655806200472668201986465266103003018370561318048070825851002395175609868205
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_rw has 20 failures.

0.chip_egret_csr_rw.110401216379061308148020993940703588570246194455999895748150828412814021424837
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_rw.50968196961901072493668808959810991036639347455908667473295471859122809937811
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 18 more failures.

Test chip_egret_csr_bit_bash has 5 failures.

0.chip_egret_csr_bit_bash.45318169217792252860632072261417942060412219497912071412005063326944027839049
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_bit_bash.72339699847765139341506305249460792391085687860130699082722198213776758365583
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_aliasing has 5 failures.

0.chip_egret_csr_aliasing.26015653327943197248079091441077501153029225283417681810222886489527075765754
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_aliasing.75717049010224355918642210575649931757911289604735077983396577133170737707709
Line 196, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

... and 2 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 88 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 88 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.36417770242816648979331211039025661552300011298410005374456125050967202100465
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2931.256832 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2931.256832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.26075979853161258619179948040095318954249134033383606872828560078005170593887
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3681.945800 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3681.945800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 86 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.113640252182429192790110401654681263218717476952335938170493667140156840747532
    Line 356, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.50977278703765586897021062817763745839391288541367887984262953062832723178414
    Line 353, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.67833699198809767927953797709917485095184004347179609348693333995975707747806
    Line 353, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.10067186219478506891134230150566926655191340786281466880545972304646163536023
    Line 356, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.86693097056743743945166247595935927389075856780708283079027033025333563960864
    Line 354, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [keymgr_key_derivation_test_sim_dv(sw/device/tests/keymgr_key_derivation_test.c:17)] CHECK-STATUS-fail: * has 6 failures:
- Test chip_sw_keymgr_key_derivation has 1 failures.
  - 0.chip_sw_keymgr_key_derivation.112116566066925279128368002596763090824517658389900403098765530073101311923714
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
```
  UVM_ERROR @ 2804.906258 us: (sw_logger_if.sv:526) [keymgr_key_derivation_test_sim_dv(sw/device/tests/keymgr_key_derivation_test.c:17)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2804.906258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_prod has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_prod.83856206326443257762220493188943371342533389075480208473612290009633972041779
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_key_derivation_prod/latest/run.log
```
  UVM_ERROR @ 3397.446268 us: (sw_logger_if.sv:526) [keymgr_key_derivation_test_sim_dv(sw/device/tests/keymgr_key_derivation_test.c:17)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 3397.446268 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_key_derivation_jitter_en has 3 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en.5379466101319707017606840757299288674212110345408743748987173855041503145695
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
  UVM_ERROR @ 2918.066559 us: (sw_logger_if.sv:526) [keymgr_key_derivation_test_sim_dv(sw/device/tests/keymgr_key_derivation_test.c:17)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2918.066559 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_key_derivation_jitter_en.88014077937172306961743053275238019184203183111778218681231637263514432754526
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_keymgr_key_derivation_jitter_en/latest/run.log
```
  UVM_ERROR @ 2760.014306 us: (sw_logger_if.sv:526) [keymgr_key_derivation_test_sim_dv(sw/device/tests/keymgr_key_derivation_test.c:17)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2760.014306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_keymgr_key_derivation_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.24337059551850006585865221484638446179242281854892291072719686217953620682521
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest/run.log
```
  UVM_ERROR @ 2917.841715 us: (sw_logger_if.sv:526) [keymgr_key_derivation_test_sim_dv(sw/device/tests/keymgr_key_derivation_test.c:17)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2917.841715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 6 failures:
- Test chip_sw_rv_dm_ndm_reset_req_when_cpu_halted has 1 failures.
  - 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.6286245897742776147107271314628887098410777737767705646312609769011348395179
    Line 334, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.68748530247567902292815026273392304767156777911636949403780409225865330370630
    Line 326, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.37617871789773071648211729936191974901120624586412679752873515969905618992964
    Line 359, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.72101034598283768592151793994640245401393715043409526219388769392403615479903
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.106941266996363882407172093191396976384199939462898790451894488188377557727252
    Line 312, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- ... and 1 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.87071388342455048559438600790147895722026198864862934615016602017377844924313
    Line 358, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.49440179297077048837963083961820298917153686967990434418772233483042023004765
    Line 356, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.74603843564566974890254686645317417257779666344985590961516073817450769194329
    Line 358, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.76966353375500486944348462993078069847568651227880266026194412641170752282115
    Line 358, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.30000986444514109823384752564296054075078235487063191043386289252171111245559
    Line 358, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ==== has 4 failures:
- Test chip_sw_spi_host_tx_rx has 4 failures.
  - 0.chip_sw_spi_host_tx_rx.13491531650401601819196939895407217414333673597858091669656877041704054496
    Line 338, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_host_tx_rx/latest/run.log
```
  UVM_ERROR @ 3181.317364 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 3181.317364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_spi_host_tx_rx.56729045274726616334410360058929118771346358626121126168220376603805486093417
    Line 343, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_spi_host_tx_rx/latest/run.log
```
  UVM_ERROR @ 2959.569810 us: (sw_test_status_if.sv:85) [tb.u_sim_sram.u_sim_sram_if.u_sw_test_status_if] ==== SW TEST FAILED ====
  UVM_INFO @ 2959.569810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_lc_signals_test.c:103)] DIF-fail: dif_otp_ctrl_dai_program*(&otp, kOtpPartitionSecret*, i, word) returns * has 4 failures:
- Test chip_sw_otp_ctrl_lc_signals_test_unlocked0 has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3808216930213882582796691215031326877707403185652604014851607036530494166063
    Line 311, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 2874.206224 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_lc_signals_test.c:103)] DIF-fail: dif_otp_ctrl_dai_program64(&otp, kOtpPartitionSecret2, i, word) returns 13
  UVM_INFO @ 2874.206224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_otp_ctrl_lc_signals_dev has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_dev.22635086632159443963753250666065793926311057890273044506957370835587987301797
    Line 312, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_dev/latest/run.log
```
  UVM_ERROR @ 3480.155967 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_lc_signals_test.c:103)] DIF-fail: dif_otp_ctrl_dai_program64(&otp, kOtpPartitionSecret2, i, word) returns 13
  UVM_INFO @ 3480.155967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_otp_ctrl_lc_signals_prod has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_prod.105116943180474361077981089606543139953437184864425139780405036939073160842525
    Line 312, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_prod/latest/run.log
```
  UVM_ERROR @ 3175.636272 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_lc_signals_test.c:103)] DIF-fail: dif_otp_ctrl_dai_program64(&otp, kOtpPartitionSecret2, i, word) returns 13
  UVM_INFO @ 3175.636272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.54068820165173925061141139258197326861498592203423120922370331657301800606404
    Line 312, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 2910.674905 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_lc_signals_test.c:103)] DIF-fail: dif_otp_ctrl_dai_program64(&otp, kOtpPartitionSecret2, i, word) returns 13
  UVM_INFO @ 2910.674905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [entropy_src_edn_reqs_test_sim_dv(sw/device/tests/entropy_src_edn_reqs_test.c:261)] CHECK-STATUS-fail: * has 4 failures:
- Test chip_sw_edn_entropy_reqs has 3 failures.
  - 0.chip_sw_edn_entropy_reqs.14651808296269867627170562577095884313927405853639572609868697947550139707458
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_edn_entropy_reqs/latest/run.log
```
  UVM_ERROR @ 3260.057220 us: (sw_logger_if.sv:526) [entropy_src_edn_reqs_test_sim_dv(sw/device/tests/entropy_src_edn_reqs_test.c:261)] CHECK-STATUS-fail: 0x00001a40
  UVM_INFO @ 3260.057220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_edn_entropy_reqs.47230544467450915184448080703732034583472092067052435735286526207651322552236
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_edn_entropy_reqs/latest/run.log
```
  UVM_ERROR @ 2598.671481 us: (sw_logger_if.sv:526) [entropy_src_edn_reqs_test_sim_dv(sw/device/tests/entropy_src_edn_reqs_test.c:261)] CHECK-STATUS-fail: 0x00001a40
  UVM_INFO @ 2598.671481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_sw_edn_entropy_reqs_jitter has 1 failures.
  - 0.chip_sw_edn_entropy_reqs_jitter.94174652551993391396110244583022204117297529927506363122324583109300859541021
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_edn_entropy_reqs_jitter/latest/run.log
```
  UVM_ERROR @ 3119.871275 us: (sw_logger_if.sv:526) [entropy_src_edn_reqs_test_sim_dv(sw/device/tests/entropy_src_edn_reqs_test.c:261)] CHECK-STATUS-fail: 0x00001a40
  UVM_INFO @ 3119.871275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 4.chip_sw_alert_handler_lpg_sleep_mode_alerts.111155585716399803646703897210311379347893812545494738333151459585221751854747
    Line 303, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.360001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 84.chip_sw_alert_handler_lpg_sleep_mode_alerts.54081018689627721455912827936125365576530064987992374125440017949851171434707
    Line 303, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.240001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 2 failures.
  - 47.chip_sw_all_escalation_resets.99045416568248509584361134904458060651142202630777553505984344436436815877442
    Line 303, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.300001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.chip_sw_all_escalation_resets.42878456812309494196549881923791856749713145471396016271707856367034721259111
    Line 303, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/51.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.260001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.103263279738655507165206463512504264607158937955682619162417250766442985127766
    Line 120, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.86260774338816198044488782863283190844447331917604414725981281508525012764742
    Line 120, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.41199586409449207279732214482856052623802533127389780663814129418725181960055
    Line 120, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_descrambling_test_sim_dv(sw/device/tests/otp_ctrl_descrambling_test.c:79)] CHECK-STATUS-fail: * has 3 failures:
- Test chip_sw_otp_ctrl_descrambling has 3 failures.
  - 0.chip_sw_otp_ctrl_descrambling.62942629715348609959114973622254400254769097593327184023899843378776409474950
    Line 325, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_descrambling/latest/run.log
```
  UVM_ERROR @ 2872.225230 us: (sw_logger_if.sv:526) [otp_ctrl_descrambling_test_sim_dv(sw/device/tests/otp_ctrl_descrambling_test.c:79)] CHECK-STATUS-fail: 0x0000002c
  UVM_INFO @ 2872.225230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_descrambling.33652864219512113328240139345714376724696209792294893979848170415874013863637
    Line 330, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_otp_ctrl_descrambling/latest/run.log
```
  UVM_ERROR @ 2296.264516 us: (sw_logger_if.sv:526) [otp_ctrl_descrambling_test_sim_dv(sw/device/tests/otp_ctrl_descrambling_test.c:79)] CHECK-STATUS-fail: 0x0000002c
  UVM_INFO @ 2296.264516 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 3 failures:
- Test chip_sw_lc_walkthrough_dev has 1 failures.
  - 0.chip_sw_lc_walkthrough_dev.80303882432880430747982894246627935066117335515995707389961823843968024278006
    Line 371, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
```
  UVM_ERROR @ 9955.506594 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 9955.506594 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_lc_walkthrough_prod has 1 failures.
  - 0.chip_sw_lc_walkthrough_prod.100902802080679239045078003806273082953530355715683748150631370586148906656869
    Line 371, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  UVM_ERROR @ 9681.165660 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 9681.165660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_lc_walkthrough_rma has 1 failures.
  - 0.chip_sw_lc_walkthrough_rma.63046504992891256344465694608820221342080417866276650224923102180393831262972
    Line 343, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
```
  UVM_ERROR @ 4895.691276 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 4895.691276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [csrng_lc_hw_debug_en_test_sim_dv(sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c:173)] DIF-fail: dif_otp_ctrl_dai_program*(&otp_ctrl, kOtpPartitionSecret*, *, otp_token_l) returns * has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.2185650256149495741241447089192019181173425677303642631741857589811719527981
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_ERROR @ 2930.870196 us: (sw_logger_if.sv:526) [csrng_lc_hw_debug_en_test_sim_dv(sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c:173)] DIF-fail: dif_otp_ctrl_dai_program64(&otp_ctrl, kOtpPartitionSecret0, 0x10, otp_token_l) returns 13
  UVM_INFO @ 2930.870196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.78263159853055478351127831028048468175115312245221595724838685605577921718308
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_ERROR @ 3248.738280 us: (sw_logger_if.sv:526) [csrng_lc_hw_debug_en_test_sim_dv(sw/device/tests/sim_dv/csrng_lc_hw_debug_en_test.c:173)] DIF-fail: dif_otp_ctrl_dai_program64(&otp_ctrl, kOtpPartitionSecret0, 0x10, otp_token_l) returns 13
  UVM_INFO @ 3248.738280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [keymgr_sideload_aes_test_sim_dv(sw/device/tests/keymgr_sideload_aes_test.c:190)] CHECK-STATUS-fail: * has 3 failures:
- Test chip_sw_keymgr_sideload_aes has 3 failures.
  - 0.chip_sw_keymgr_sideload_aes.95094588528659918104424760806826124762160427384279531056831977679283527453727
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @ 3079.915956 us: (sw_logger_if.sv:526) [keymgr_sideload_aes_test_sim_dv(sw/device/tests/keymgr_sideload_aes_test.c:190)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 3079.915956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_sideload_aes.44123617315022829225934117468868355515535969480539067280977201132514692933589
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_keymgr_sideload_aes/latest/run.log
```
  UVM_ERROR @ 2987.357940 us: (sw_logger_if.sv:526) [keymgr_sideload_aes_test_sim_dv(sw/device/tests/keymgr_sideload_aes_test.c:190)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2987.357940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [keymgr_sideload_acc_test_sim_dv(sw/device/tests/keymgr_sideload_acc_test.c:193)] CHECK-STATUS-fail: * has 3 failures:
- Test chip_sw_keymgr_sideload_acc has 3 failures.
  - 0.chip_sw_keymgr_sideload_acc.31904581755181298809528171726794847280768080038531873218381255133663101649901
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_sideload_acc/latest/run.log
```
  UVM_ERROR @ 2394.070898 us: (sw_logger_if.sv:526) [keymgr_sideload_acc_test_sim_dv(sw/device/tests/keymgr_sideload_acc_test.c:193)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2394.070898 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_keymgr_sideload_acc.6988694280958232979402496802698882156510019562547744248257023258985412042652
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_keymgr_sideload_acc/latest/run.log
```
  UVM_ERROR @ 2584.583112 us: (sw_logger_if.sv:526) [keymgr_sideload_acc_test_sim_dv(sw/device/tests/keymgr_sideload_acc_test.c:193)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 2584.583112 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:139) [chip_sw_power_virus_vseq] Check failed device_rsp_q.size() == * (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.41579071042632610112385248320557909983384751345997601270804701920087396147222
    Line 367, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4157.026738 us: (chip_sw_power_virus_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4157.026738 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.38433387195085358311280653500688665802890218891248428037384038385368475356378
    Line 362, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4082.125477 us: (chip_sw_power_virus_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4082.125477 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.87954059315865726428089155867429217837390353350495602281376040103589658617873
    Line 330, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.105234737558928802522702837945656554931858883156836509378137616215857155920198
    Line 331, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.105104511548996844106792627824580956539078186993654857255883749016698060376983
    Line 329, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.80087006396026950167521635023756292098496307944909580842283564594697303735610
Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  ---- STDERR ----
  WARNING: Output base '/nfshome/luism/.cache/bazel/_bazel_luism/c44fc6b1221d566af8bd7ea3631efcfb' is on NFS. This may lead to surprising failures and undetermined behavior.
  Another command (pid=3694332) is running. Waiting for it to complete on the server (server_pid=649715)...
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nfshome/luism/claude-dv-home/pavona/pavona-work/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nfshome/luism/claude-dv-home/pavona/pavona-work/sw/device/tests/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/nfshome/luism/claude-dv-home/pavona/pavona-work/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.63124892060482642358600182725447895904463885308376318145713272240752436447457
Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  ---- STDERR ----
  WARNING: Output base '/nfshome/luism/.cache/bazel/_bazel_luism/c44fc6b1221d566af8bd7ea3631efcfb' is on NFS. This may lead to surprising failures and undetermined behavior.
  Another command (pid=136647) is running. Waiting for it to complete on the server (server_pid=649715)...
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nfshome/luism/claude-dv-home/pavona/pavona-work/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nfshome/luism/claude-dv-home/pavona/pavona-work/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/nfshome/luism/claude-dv-home/pavona/pavona-work/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.90796631463663867409505679109157462738727837597391049338396260204746394951418
    Line 365, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.28838133455968567708234594730966350337973548456446783367443165389606113763009
    Line 331, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.67410509050194225408253455949258064549956888921900547126738872110685203562375
    Line 367, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.114318692491994083590551830668764516400037066832651540145135455509738825465531
    Line 330, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred! has 2 failures:
- Test rom_e2e_asm_init_prod has 1 failures.
  - 0.rom_e2e_asm_init_prod.72435130258029453241851450837947024031599588110649441358103265757877710287895
    Line 313, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_asm_init_prod/latest/run.log
```
  UVM_FATAL @ 10010.140001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
  UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_asm_init_prod_end has 1 failures.
  - 0.rom_e2e_asm_init_prod_end.63365706859841006340792972017880585099311883352378987328155502936752366685056
    Line 313, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
```
  UVM_FATAL @ 10010.120001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
  UVM_INFO @ 10010.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [inject_scramble_seed_sim_dv(sw/device/tests/sim_dv/inject_scramble_seed.c:99)] DIF-fail: dif_otp_ctrl_is_digest_computed(&otp_ctrl, kOtpPartitionSecret*, &secret1_locked) returns * has 1 failures:
- Test chip_sw_inject_scramble_seed has 1 failures.
  - 0.chip_sw_inject_scramble_seed.59016929408284275288479699118672982037930656769291325638954235123611178836782
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log
```
  UVM_ERROR @ 3236.841912 us: (sw_logger_if.sv:526) [inject_scramble_seed_sim_dv(sw/device/tests/sim_dv/inject_scramble_seed.c:99)] DIF-fail: dif_otp_ctrl_is_digest_computed(&otp_ctrl, kOtpPartitionSecret1, &secret1_locked) returns 3
  UVM_INFO @ 3236.841912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_vseq.sv:124) [chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_spi_device_pass_through has 1 failures.
  - 0.chip_sw_spi_device_pass_through.112610491266449976547141595990370399678169379585462793135135297661353383587020
    Line 320, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
```
  UVM_ERROR @ 3136.098624 us: (chip_sw_spi_passthrough_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_vseq] Check failed device_rsp_q.size() == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 3136.098624 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:172) [chip_sw_spi_passthrough_collision_vseq] Check failed host_rsp_q.size() == device_rsp_q.size() (* [*] vs * [*]) has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.8428457684348146292093353804632362424128412373451706239462489761628754770660
    Line 322, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3472.058852 us: (chip_sw_spi_passthrough_collision_vseq.sv:172) [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Check failed host_rsp_q.size() == device_rsp_q.size() (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 3472.058852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 1 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 1 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.4447728683521091445516248780176820966717203951914955780973647968839599718148
    Line 311, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 2750.440650 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
  UVM_INFO @ 2750.440650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.40905336081197845437024503322547814653312769254953261301101154859332337210891
    Line 318, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2745.033138 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2745.033138 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_mem_access_test_sim_dv(sw/device/tests/otp_ctrl_mem_access_test.c:59)] DIF-fail: Failed to program word kTestData[*] = *. has 1 failures:
- Test chip_sw_otp_ctrl_dai_lock has 1 failures.
  - 0.chip_sw_otp_ctrl_dai_lock.104536225285374386319384607459074968410904336852476306655806481000798060662869
    Line 311, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_dai_lock/latest/run.log
```
  UVM_ERROR @ 2298.227000 us: (sw_logger_if.sv:526) [otp_ctrl_mem_access_test_sim_dv(sw/device/tests/otp_ctrl_mem_access_test.c:59)] DIF-fail: Failed to program word kTestData[0] = 0x11112222.
  UVM_INFO @ 2298.227000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.112183718402050138871984730865856985238954266867754083647664780720228759453992
    Line 284, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_vendor_test_ecc_error_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_vendor_test_ecc_error_test.c:70)] CHECK-STATUS-fail: * has 1 failures:
- Test chip_sw_otp_ctrl_ecc_error_vendor_test has 1 failures.
  - 0.chip_sw_otp_ctrl_ecc_error_vendor_test.5375418133588247989433424647020212308095257462627435052912159209035623775168
    Line 312, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest/run.log
```
  UVM_ERROR @ 2877.236819 us: (sw_logger_if.sv:526) [otp_ctrl_vendor_test_ecc_error_test_sim_dv(sw/device/tests/sim_dv/otp_ctrl_vendor_test_ecc_error_test.c:70)] CHECK-STATUS-fail: 0x00000980
  UVM_INFO @ 2877.236819 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@132850) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.106570553255131746634129337148790894663243528805183600847798352030997872294367
Line 335, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5050.593111 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@132850) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  a_blocked: 'h0  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
  UVM_INFO @ 5050.593111 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.

0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.91215331087741957905979483286822306316614073169829540854981652346576385153154
Line 343, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_egret.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 8476009320ps failed at 8476009320ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_egret.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 8476092648ps failed at 8476092648ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for i == *kTestPhase has 1 failures:
- Test chip_sw_sysrst_ctrl_inputs has 1 failures.
  - 0.chip_sw_sysrst_ctrl_inputs.63807959333614426514039840314854622047543088154949244642571870658368021803062
    Line 317, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest/run.log
```
  UVM_ERROR @ 3347.247746 us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after 10 usec (1000 CPU cycles) waiting for i == *kTestPhase
  UVM_INFO @ 3347.247746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.74235883265058793088976044124973630996355120628566139026408220807051545889530
    Line 334, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34527.672709 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
  
  UVM_INFO @ 34527.672709 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:321)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.25142738003936604526206941878532352303985251147870722466086185567124961549703
    Line 309, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2856.190996 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:321)] CHECK-fail: Expect alert 44!
  UVM_INFO @ 2856.190996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after running for * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.111214122063721973821043588213019632839667175774923579621125521607872307627534
    Log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after running for 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [csrng_fuse_en_sw_app_read_sim_dv(sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read.c:79)] DIF-fail: dif_otp_ctrl_dai_read_start(&otp, kOtpPartitionHwCfg*, kOtpIfetchHwRelativeOffset) returns * has 1 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.97925324908397490659247877471518439496834672338236272378061194311467902335678
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_ERROR @ 2787.393754 us: (sw_logger_if.sv:526) [csrng_fuse_en_sw_app_read_sim_dv(sw/device/tests/sim_dv/csrng_fuse_en_sw_app_read.c:79)] DIF-fail: dif_otp_ctrl_dai_read_start(&otp, kOtpPartitionHwCfg1, kOtpIfetchHwRelativeOffset) returns 11
  UVM_INFO @ 2787.393754 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [keymgr_sideload_kmac_test_sim_dv(sw/device/tests/keymgr_sideload_kmac_test.c:228)] CHECK-STATUS-fail: * has 1 failures:
- Test chip_sw_keymgr_sideload_kmac has 1 failures.
  - 0.chip_sw_keymgr_sideload_kmac.70495612609140464170125958692881469736491289630305527203893027980982432625166
    Line 310, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_keymgr_sideload_kmac/latest/run.log
```
  UVM_ERROR @ 3503.397395 us: (sw_logger_if.sv:526) [keymgr_sideload_kmac_test_sim_dv(sw/device/tests/keymgr_sideload_kmac_test.c:228)] CHECK-STATUS-fail: 0x00000fa0
  UVM_INFO @ 3503.397395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sram_ctrl_execution_main_test_sim_dv(sw/device/tests/sim_dv/sram_ctrl_execution_main_test.c:73)] DIF-fail: dif_otp_ctrl_dai_read_start(&otp, kOtpPartitionHwCfg*, kOtpIfetchHwRelativeOffset) returns * has 1 failures:
- Test chip_sw_sram_ctrl_execution_main has 1 failures.
  - 0.chip_sw_sram_ctrl_execution_main.63404415973085980473623920931690661180103940747226567817859852259195241325549
    Line 311, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_ERROR @ 3104.685326 us: (sw_logger_if.sv:526) [sram_ctrl_execution_main_test_sim_dv(sw/device/tests/sim_dv/sram_ctrl_execution_main_test.c:73)] DIF-fail: dif_otp_ctrl_dai_read_start(&otp, kOtpPartitionHwCfg1, kOtpIfetchHwRelativeOffset) returns 11
  UVM_INFO @ 3104.685326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 1 failures:
- Test chip_sw_clkmgr_jitter_frequency has 1 failures.
  - 0.chip_sw_clkmgr_jitter_frequency.75550640369176080721975158156594718654957125325186745440058121097604223752635
    Line 350, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log
```
  UVM_ERROR @ 3292.468329 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
  UVM_INFO @ 3292.468329 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. has 1 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 1 failures.
  - 0.chip_sw_rv_dm_access_after_wakeup.10178554838795396797938577809047404459446139435413663970467577792227227937845
    Line 336, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 13043.106587 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.
  UVM_INFO @ 13043.106587 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.949095089225809074829331278049988209791103927932295764066009775332329182435
    Line 287, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 9570.565914 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10740 read out mismatch
  UVM_INFO @ 9570.565914 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.25390237370352467824222722216702466912142619334754914873778623191795716093956
    Line 319, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3590.905000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3590.905000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.80271101986257518495934255658659790421448144947578236665650439395037059299117
    Line 325, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3992.428000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3992.428000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.97647225985516736456475884840256389759153186343710478921057033961468557832098
    Line 334, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 14317.941184 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
  UVM_INFO @ 14317.941184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 1 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.43544398033254203651898073675546892972745574653646646998539736157216163643965
    Line 341, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest/run.log
```
  UVM_ERROR @ 100018.511395 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 100000000 ns
  
  UVM_INFO @ 100018.511395 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.76498064321378508659502168517049838815270530118142502766643085168906831505816
    Line 330, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4843506197948703120445762548993564077168403876540501743782981255662225569762
    Line 329, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.10099038585907562228748992237808865158670659512856428411136007709006464265408
    Line 337, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 14353.193243 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 14353.193243 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest(&otp_ctrl, kOtpPartitionCreatorSwCfg, &creator_digest) returns * has 1 failures:
- Test rom_e2e_keymgr_init_rom_ext_meas has 1 failures.
  - 0.rom_e2e_keymgr_init_rom_ext_meas.58700181802740069517307692033614153387555169088441792280599013453084176237692
    Line 326, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log
```
  UVM_ERROR @ 17815.323043 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest(&otp_ctrl, kOtpPartitionCreatorSwCfg, &creator_digest) returns 3
  UVM_INFO @ 17815.323043 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest(&otp_ctrl, kOtpPartitionCreatorSwCfg, &creator_digest) returns * has 1 failures:
- Test rom_e2e_keymgr_init_rom_ext_no_meas has 1 failures.
  - 0.rom_e2e_keymgr_init_rom_ext_no_meas.110207495028233075680115189332330094302542390589977981012302305742366316407544
    Line 326, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log
```
  UVM_ERROR @ 17708.229540 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest(&otp_ctrl, kOtpPartitionCreatorSwCfg, &creator_digest) returns 3
  UVM_INFO @ 17708.229540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:61)] CHECK-STATUS-fail: * has 1 failures:
- Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 1 failures.
  - 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.84276527984942352516332400032849029406850764256717358490202697074599397817806
    Line 327, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log
```
  UVM_ERROR @ 15435.833800 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:61)] CHECK-STATUS-fail: 0x00000860
  UVM_INFO @ 15435.833800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.114983100348709114102747379387628723343201774895038094299375985773290225704223
    Line 329, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 14832.272526 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 14832.272526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [keymgr_functest_sim_dv(sw/device/silicon_creator/lib/drivers/keymgr_functest.c:123)] DIF-fail: dif_otp_ctrl_is_digest_computed(otp, kOtpPartitionSecret*, &is_computed) returns * has 1 failures:
- Test rom_keymgr_functest has 1 failures.
  - 0.rom_keymgr_functest.40402670787201544937597290293904346231578216536775703663815200997506856327533
    Line 315, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/0.rom_keymgr_functest/latest/run.log
```
  UVM_ERROR @ 2831.982901 us: (sw_logger_if.sv:526) [keymgr_functest_sim_dv(sw/device/silicon_creator/lib/drivers/keymgr_functest.c:123)] DIF-fail: dif_otp_ctrl_is_digest_computed(otp, kOtpPartitionSecret2, &is_computed) returns 3
  UVM_INFO @ 2831.982901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred! has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 2.rom_e2e_shutdown_output.79348206911723110487807820763135939700229691130922893773273228260886709868152
    Line 341, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/2.rom_e2e_shutdown_output/latest/run.log
```
  UVM_FATAL @ 25979.951918 us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!
  UVM_INFO @ 25979.951918 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.

4.chip_sw_rv_core_ibex_lockstep_glitch.12693784389452888900690404597350046865702819056946347298050339284902760925377
Line 320, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/chip_egret-sim-vcs/4.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  UVM_INFO @ 3007.208644 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:636) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Checking for potential alert in cycle 2.
  UVM_INFO @ 3007.208644 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:725) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Expecting an internal major alert due to glitched output.
  UVM_INFO @ 3007.218644 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:636) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Checking for potential alert in cycle 3.
  UVM_INFO @ 3007.228644 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:636) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Checking for potential alert in cycle 4.