CLKMGR/DRAGONFLY Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.170s	5.033s	98.037us	3	3	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.670s	3.827s	19.293us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	4.610s	8.062s	380.928us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	0.980s	4.929s	60.358us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.810s	7.113s	312.389us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
		clkmgr_csr_aliasing	0.980s	4.929s	60.358us	5	5	100.00
V1		TOTAL				58	58	100.00
V2	peri_enables	clkmgr_peri	0.860s	4.404s	49.163us	3	3	100.00
V2	trans_enables	clkmgr_trans	0.560s	4.390s	13.975us	1	1	100.00
V2	clk_status	clkmgr_clk_status	0.780s	4.378s	54.608us	3	3	100.00
V2	jitter	clkmgr_smoke	1.170s	5.033s	98.037us	3	3	100.00
V2	frequency	clkmgr_frequency	0.980s	4.422s	40.290us	1	1	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	0.520s	4.413s	4.835us	0	1	0.00
V2	frequency_overflow	clkmgr_frequency	0.980s	4.422s	40.290us	1	1	100.00
V2	stress_all	clkmgr_stress_all	1.740s	5.651s	149.147us	0	1	0.00
V2	intr_test	clkmgr_intr_test				0	0	--
V2	alert_test	clkmgr_alert_test	0.650s	4.313s	22.566us	3	3	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.990s	8.792s	345.638us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.990s	8.792s	345.638us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.670s	3.827s	19.293us	5	5	100.00
		clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
		clkmgr_csr_aliasing	0.980s	4.929s	60.358us	5	5	100.00
		clkmgr_same_csr_outstanding	2.300s	6.034s	239.336us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.670s	3.827s	19.293us	5	5	100.00
		clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
		clkmgr_csr_aliasing	0.980s	4.929s	60.358us	5	5	100.00
		clkmgr_same_csr_outstanding	2.300s	6.034s	239.336us	20	20	100.00
V2		TOTAL				51	53	96.23
V2S	tl_intg_err	clkmgr_sec_cm	5.400s	9.827s	617.021us	3	3	100.00
		clkmgr_tl_intg_err	3.370s	7.268s	337.288us	4	4	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	0.990s	6.156s	62.855us	4	4	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	0.990s	6.156s	62.855us	4	4	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	0.990s	6.156s	62.855us	4	4	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	0.990s	6.156s	62.855us	4	4	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	2.620s	7.285s	295.060us	3	3	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.370s	7.268s	337.288us	4	4	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	0.980s	4.422s	40.290us	1	1	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	0.520s	4.413s	4.835us	0	1	0.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	0.990s	6.156s	62.855us	4	4	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.440s	5.006s	122.538us	3	3	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	5.400s	9.827s	617.021us	3	3	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.050s	6.334s	88.980us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	5.400s	9.827s	617.021us	3	3	100.00
V2S		TOTAL				17	17	100.00
V3	regwen	clkmgr_regwen	1.090s	4.361s	45.681us	4	4	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	47.080s	50.862s	4.219ms	2	3	66.67
V3		TOTAL				6	7	85.71
		TOTAL				132	135	97.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	10	9	7	70.00
V2S	5	5	5	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	98.53	94.51	100.00	100.00	98.23	96.07	87.26

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* has 2 failures:

  • Test clkmgr_frequency_timeout has 1 failures.

    • 0.clkmgr_frequency_timeout.101665229876021477540499266174922905105057247187584375911840520341527394821515
      Line 79, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/clkmgr_top_dragonfly-sim-vcs/0.clkmgr_frequency_timeout/latest/run.log

        UVM_ERROR @   4834655 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @   4834655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all has 1 failures.

    • 0.clkmgr_stress_all.11123543788709474174015972096801457015536491856571096737372895502551828809775
      Line 157, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/clkmgr_top_dragonfly-sim-vcs/0.clkmgr_stress_all/latest/run.log

        UVM_ERROR @ 149146696 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b01, got 0b00
        UVM_INFO @ 149146696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_frequency_timeout_vseq.sv:113) [clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (* [*] vs * [*]) expected some alerts to fire has 1 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 2.clkmgr_stress_all_with_rand_reset.106641176128816261598148919748843235637197068919220683004604508789564267225872
      Line 88, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/clkmgr_top_dragonfly-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  89701854 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (14 [0xe] vs 14 [0xe]) expected some alerts to fire
        UVM_INFO @  89701854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---