CLKMGR/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	0.640s	4.649s	19.152us	1	1	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.610s	4.399s	42.246us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.780s	11.894s	1.905ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.150s	4.357s	55.878us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.340s	4.554s	164.854us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
		clkmgr_csr_aliasing	1.150s	4.357s	55.878us	5	5	100.00
V1		TOTAL				39	39	100.00
V2	peri_enables	clkmgr_peri	0.530s	4.487s	18.852us	1	1	100.00
V2	trans_enables	clkmgr_trans	0.480s	4.463s	16.456us	1	1	100.00
V2	extclk	clkmgr_extclk	1.030s	4.612s	198.054us	1	1	100.00
V2	clk_status	clkmgr_clk_status	0.670s	4.452s	42.209us	3	3	100.00
V2	jitter	clkmgr_smoke	0.640s	4.649s	19.152us	1	1	100.00
V2	frequency	clkmgr_frequency	4.950s	9.072s	1.788ms	1	1	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	0.890s	4.497s	143.068us	1	1	100.00
V2	frequency_overflow	clkmgr_frequency	4.950s	9.072s	1.788ms	1	1	100.00
V2	stress_all	clkmgr_stress_all	23.790s	27.729s	5.284ms	3	3	100.00
V2	intr_test	clkmgr_intr_test				0	0	--
V2	alert_test	clkmgr_alert_test	0.630s	4.477s	73.051us	3	3	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.690s	7.591s	918.902us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.690s	7.591s	918.902us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.610s	4.399s	42.246us	5	5	100.00
		clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
		clkmgr_csr_aliasing	1.150s	4.357s	55.878us	5	5	100.00
		clkmgr_same_csr_outstanding	1.130s	4.526s	174.127us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.610s	4.399s	42.246us	5	5	100.00
		clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
		clkmgr_csr_aliasing	1.150s	4.357s	55.878us	5	5	100.00
		clkmgr_same_csr_outstanding	1.130s	4.526s	174.127us	20	20	100.00
V2		TOTAL				54	54	100.00
V2S	tl_intg_err	clkmgr_sec_cm	3.650s	7.028s	1.280ms	4	4	100.00
		clkmgr_tl_intg_err	1.990s	5.525s	253.290us	8	8	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	1.600s	5.442s	156.492us	6	6	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	1.600s	5.442s	156.492us	6	6	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	1.600s	5.442s	156.492us	6	6	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	1.600s	5.442s	156.492us	6	6	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.320s	6.726s	912.503us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	1.990s	5.525s	253.290us	8	8	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	4.950s	9.072s	1.788ms	1	1	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	0.890s	4.497s	143.068us	1	1	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	1.600s	5.442s	156.492us	6	6	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	0.790s	4.441s	95.946us	3	3	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	0.600s	4.431s	52.552us	1	1	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	0.580s	4.421s	20.670us	3	3	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	0.670s	4.897s	45.190us	4	4	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	0.570s	4.397s	35.798us	1	1	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.650s	7.028s	1.280ms	4	4	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.550s	4.275s	18.092us	3	3	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.650s	7.028s	1.280ms	4	4	100.00
V2S		TOTAL				50	50	100.00
V3	regwen	clkmgr_regwen	4.420s	8.270s	1.202ms	6	6	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	48.270s	51.881s	13.092ms	3	3	100.00
V3		TOTAL				9	9	100.00
		TOTAL				152	152	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	10	10	90.91
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.01	99.34	96.26	100.00	100.00	99.17	96.47	87.82

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22