CSRNG Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke csrng_smoke 2.720s 6.321s 194.865us 5 5 100.00
V1 csr_hw_reset csrng_csr_hw_reset 1.340s 5.539s 63.468us 5 5 100.00
V1 csr_rw csrng_csr_rw 1.490s 5.466s 89.092us 20 20 100.00
V1 csr_bit_bash csrng_csr_bit_bash 20.650s 24.272s 981.372us 5 5 100.00
V1 csr_aliasing csrng_csr_aliasing 3.280s 6.526s 197.634us 5 5 100.00
V1 csr_mem_rw_with_rand_reset csrng_csr_mem_rw_with_rand_reset 4.690s 8.316s 394.705us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr csrng_csr_rw 1.490s 5.466s 89.092us 20 20 100.00
csrng_csr_aliasing 3.280s 6.526s 197.634us 5 5 100.00
V1 TOTAL 60 60 100.00
V2 interrupts csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
V2 alerts csrng_alert 16.160s 19.574s 1.146ms 14 14 100.00
V2 err csrng_err 1.770s 5.580s 139.258us 52 52 100.00
V2 cmds csrng_cmds 5.314m 5.376m 31.568ms 9 9 100.00
V2 life cycle csrng_cmds 5.314m 5.376m 31.568ms 9 9 100.00
V2 stress_all csrng_stress_all 10.911m 10.961m 33.019ms 5 5 100.00
V2 intr_test csrng_intr_test 2.110s 5.362s 160.370us 50 50 100.00
V2 alert_test csrng_alert_test 1.270s 5.581s 55.942us 3 3 100.00
V2 tl_d_oob_addr_access csrng_tl_errors 8.430s 12.052s 744.167us 20 20 100.00
V2 tl_d_illegal_access csrng_tl_errors 8.430s 12.052s 744.167us 20 20 100.00
V2 tl_d_outstanding_access csrng_csr_hw_reset 1.340s 5.539s 63.468us 5 5 100.00
csrng_csr_rw 1.490s 5.466s 89.092us 20 20 100.00
csrng_csr_aliasing 3.280s 6.526s 197.634us 5 5 100.00
csrng_same_csr_outstanding 2.400s 5.442s 92.842us 3 3 100.00
V2 tl_d_partial_access csrng_csr_hw_reset 1.340s 5.539s 63.468us 5 5 100.00
csrng_csr_rw 1.490s 5.466s 89.092us 20 20 100.00
csrng_csr_aliasing 3.280s 6.526s 197.634us 5 5 100.00
csrng_same_csr_outstanding 2.400s 5.442s 92.842us 3 3 100.00
V2 TOTAL 179 179 100.00
V2S tl_intg_err csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
csrng_tl_intg_err 5.600s 9.072s 437.281us 6 6 100.00
V2S sec_cm_config_regwen csrng_regwen 0.970s 4.728s 31.575us 3 3 100.00
csrng_csr_rw 1.490s 5.466s 89.092us 20 20 100.00
V2S sec_cm_config_mubi csrng_alert 16.160s 19.574s 1.146ms 14 14 100.00
V2S sec_cm_intersig_mubi csrng_stress_all 10.911m 10.961m 33.019ms 5 5 100.00
V2S sec_cm_main_sm_fsm_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_updrsp_fsm_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_update_fsm_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_blk_enc_fsm_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_outblk_fsm_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_gen_cmd_ctr_redun csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_drbg_upd_ctr_redun csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_drbg_gen_ctr_redun csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_ctrl_mubi csrng_alert 16.160s 19.574s 1.146ms 14 14 100.00
V2S sec_cm_main_sm_ctr_local_esc csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
V2S sec_cm_constants_lc_gated csrng_stress_all 10.911m 10.961m 33.019ms 5 5 100.00
V2S sec_cm_sw_genbits_bus_consistency csrng_alert 16.160s 19.574s 1.146ms 14 14 100.00
V2S sec_cm_tile_link_bus_integrity csrng_tl_intg_err 5.600s 9.072s 437.281us 6 6 100.00
V2S sec_cm_aes_cipher_fsm_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_aes_cipher_fsm_redun csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
V2S sec_cm_aes_cipher_ctrl_sparse csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
V2S sec_cm_aes_cipher_fsm_local_esc csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
V2S sec_cm_aes_cipher_ctr_redun csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
csrng_sec_cm 2.620s 7.375s 140.879us 3 3 100.00
V2S sec_cm_aes_cipher_data_reg_local_esc csrng_intr 11.600s 15.241s 960.804us 23 23 100.00
csrng_err 1.770s 5.580s 139.258us 52 52 100.00
V2S TOTAL 12 12 100.00
V3 stress_all_with_rand_reset csrng_stress_all_with_rand_reset 3.587m 3.649m 15.299ms 3 3 100.00
V3 TOTAL 3 3 100.00
TOTAL 254 254 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 9 9 9 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.13 98.97 94.49 99.19 73.68 98.39 95.47 91.73

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22