DMA Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: `2aab100d17`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.990s	8.292s	691.846us	25	25	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.520s	8.093s	1.352ms	3	3	100.00
V1	dma_generic_smoke	dma_generic_smoke	5.470s	9.142s	2.450ms	50	50	100.00
V1	csr_hw_reset	dma_csr_hw_reset	0.830s	4.347s	109.862us	5	5	100.00
V1	csr_rw	dma_csr_rw	0.810s	4.546s	32.481us	20	20	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.090s	13.014s	1.981ms	5	5	100.00
V1	csr_aliasing	dma_csr_aliasing	5.390s	8.829s	874.612us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.180s	4.426s	104.159us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	0.810s	4.546s	32.481us	20	20	100.00
		dma_csr_aliasing	5.390s	8.829s	874.612us	5	5	100.00
V1		TOTAL				133	133	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.093m	1.155m	21.451ms	3	3	100.00
V2	dma_memory_tl_error	dma_memory_stress	13.860m	13.919m	139.736ms	6	7	85.71
V2	dma_handshake_tl_error	dma_handshake_stress	34.990m	35.043m	356.730ms	7	7	100.00
V2	dma_handshake_stress	dma_handshake_stress	34.990m	35.043m	356.730ms	7	7	100.00
V2	dma_memory_stress	dma_memory_stress	13.860m	13.919m	139.736ms	6	7	85.71
V2	dma_generic_stress	dma_generic_stress	28.120m	28.183m	342.235ms	8	8	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	34.990m	35.043m	356.730ms	7	7	100.00
V2	dma_abort	dma_abort	11.120s	14.436s	4.090ms	4	4	100.00
V2	dma_stress_all	dma_stress_all	4.646m	4.700m	28.122ms	2	5	40.00
V2	alert_test	dma_alert_test	0.610s	4.112s	13.897us	3	3	100.00
V2	intr_test	dma_intr_test	0.630s	4.355s	40.714us	4	4	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	1.920s	5.430s	269.198us	5	5	100.00
V2	tl_d_illegal_access	dma_tl_errors	1.920s	5.430s	269.198us	5	5	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	0.830s	4.347s	109.862us	5	5	100.00
		dma_csr_rw	0.810s	4.546s	32.481us	20	20	100.00
		dma_csr_aliasing	5.390s	8.829s	874.612us	5	5	100.00
		dma_same_csr_outstanding	1.470s	5.221s	186.581us	3	3	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	0.830s	4.347s	109.862us	5	5	100.00
		dma_csr_rw	0.810s	4.546s	32.481us	20	20	100.00
		dma_csr_aliasing	5.390s	8.829s	874.612us	5	5	100.00
		dma_same_csr_outstanding	1.470s	5.221s	186.581us	3	3	100.00
V2		TOTAL				45	49	91.84
V2S	dma_illegal_addr_range	dma_mem_enabled	15.470s	19.150s	267.524us	10	10	100.00
		dma_generic_stress	28.120m	28.183m	342.235ms	8	8	100.00
		dma_handshake_stress	34.990m	35.043m	356.730ms	7	7	100.00
V2S	dma_config_lock	dma_config_lock	5.650s	9.199s	1.552ms	3	3	100.00
V2S	tl_intg_err	dma_tl_intg_err	2.680s	6.310s	233.323us	3	3	100.00
		dma_sec_cm	0.600s	4.128s	10.873us	5	5	100.00
V2S		TOTAL				21	21	100.00
V3		TOTAL				0	0	--
	Unmapped tests	dma_short_transfer	2.469m	2.535m	14.938ms	15	15	100.00
		dma_longer_transfer	6.720s	10.285s	1.621ms	5	5	100.00
		dma_stress_all_with_rand_reset	12.270s	15.403s	597.485us	0	1	0.00
		TOTAL				219	224	97.77

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	3	3	2	66.67
V1	8	8	8	100.00
V2	10	10	8	80.00
V2S	4	4	4	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.27	97.31	95.77	80.45	85.96	95.89	95.86	80.64

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

UVM_FATAL @ *ps: (dma_base_vseq.sv:761) virtual_sequencer [dma_stress_all_vseq] ERROR: Timeout Condition Reached at * cycles has 3 failures:

Test dma_stress_all has 3 failures.

0.dma_stress_all.22157952500022801821646908691382950451864536581549225402961450492440599381285
Line 268, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/dma-sim-vcs/0.dma_stress_all/latest/run.log

  UVM_FATAL @ 98363610620ps: (dma_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.dma_stress_all_vseq] ERROR: Timeout Condition Reached at       10000 cycles
  UVM_INFO @ 98363610620ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.dma_stress_all.55282980937035615475032164051347823498186586287239207265859601883174632663158
Line 729, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/dma-sim-vcs/3.dma_stress_all/latest/run.log

  UVM_FATAL @ 28122184708ps: (dma_base_vseq.sv:761) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.dma_stress_all_vseq] ERROR: Timeout Condition Reached at       10000 cycles
  UVM_INFO @ 28122184708ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test dma_stress_all_with_rand_reset has 1 failures.
  - 0.dma_stress_all_with_rand_reset.35603041454004484425911522811126736228884493619734306766984207735056077943442
    Line 97, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/dma-sim-vcs/0.dma_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  597485097ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @  597485097ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_memory_stress_vseq] Check failed (dma_config.is_valid_config) has 1 failures:
- Test dma_memory_stress has 1 failures.
  - 4.dma_memory_stress.11195930322014037157798962687467921927876864138136660124139753775332007229124
    Line 206, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/dma-sim-vcs/4.dma_memory_stress/latest/run.log
```
  UVM_ERROR @ 122636744986ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_memory_stress_vseq] Check failed (dma_config.is_valid_config)
  UVM_INFO @ 122636744986ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```