EDN/EDN0 Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.630s	4.475s	45.426us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.710s	5.023s	18.737us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.690s	5.169s	19.425us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.140s	9.025s	442.750us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.000s	5.299s	224.107us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.370s	6.495s	87.930us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.690s	5.169s	19.425us	20	20	100.00
		edn_csr_aliasing	1.000s	5.299s	224.107us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	firmware	edn_genbits	1.720s	5.358s	197.954us	8	8	100.00
V2	csrng_commands	edn_genbits	1.720s	5.358s	197.954us	8	8	100.00
V2	genbits	edn_genbits	1.720s	5.358s	197.954us	8	8	100.00
V2	interrupts	edn_intr	0.740s	4.542s	20.937us	7	7	100.00
V2	alerts	edn_alert	0.890s	4.826s	29.653us	21	21	100.00
V2	errs	edn_err	0.840s	4.539s	20.125us	6	6	100.00
V2	disable	edn_disable	0.640s	4.555s	14.285us	13	13	100.00
		edn_disable_auto_req_mode	0.980s	4.672s	48.551us	8	8	100.00
V2	stress_all	edn_stress_all	2.130s	5.420s	288.669us	1	1	100.00
V2	intr_test	edn_intr_test	0.770s	6.193s	32.851us	50	50	100.00
V2	alert_test	edn_alert_test	0.710s	4.617s	24.595us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.860s	7.743s	2.300ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.860s	7.743s	2.300ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.710s	5.023s	18.737us	5	5	100.00
		edn_csr_rw	0.690s	5.169s	19.425us	20	20	100.00
		edn_csr_aliasing	1.000s	5.299s	224.107us	5	5	100.00
		edn_same_csr_outstanding	0.780s	4.981s	18.463us	3	3	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.710s	5.023s	18.737us	5	5	100.00
		edn_csr_rw	0.690s	5.169s	19.425us	20	20	100.00
		edn_csr_aliasing	1.000s	5.299s	224.107us	5	5	100.00
		edn_same_csr_outstanding	0.780s	4.981s	18.463us	3	3	100.00
V2		TOTAL				140	140	100.00
V2S	tl_intg_err	edn_sec_cm	5.600s	8.953s	485.360us	3	3	100.00
		edn_tl_intg_err	1.770s	5.280s	434.675us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.700s	4.531s	19.179us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	0.890s	4.826s	29.653us	21	21	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.600s	8.953s	485.360us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.600s	8.953s	485.360us	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.600s	8.953s	485.360us	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.600s	8.953s	485.360us	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.890s	4.826s	29.653us	21	21	100.00
		edn_sec_cm	5.600s	8.953s	485.360us	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.890s	4.826s	29.653us	21	21	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.770s	5.280s	434.675us	3	3	100.00
V2S		TOTAL				16	16	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	43.480s	46.575s	3.009ms	5	5	100.00
V3		TOTAL				5	5	100.00
		TOTAL				217	217	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.40	98.91	94.14	97.12	83.87	96.51	97.61	92.66

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22