EDN/EDN1 Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.650s	4.552s	17.772us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.630s	4.539s	20.494us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.610s	4.821s	17.415us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.890s	8.036s	3.490ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	0.910s	4.523s	36.921us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.140s	4.833s	29.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.610s	4.821s	17.415us	20	20	100.00
		edn_csr_aliasing	0.910s	4.523s	36.921us	5	5	100.00
V1		TOTAL				56	56	100.00
V2	firmware	edn_genbits	1.860s	5.533s	146.143us	8	8	100.00
V2	csrng_commands	edn_genbits	1.860s	5.533s	146.143us	8	8	100.00
V2	genbits	edn_genbits	1.860s	5.533s	146.143us	8	8	100.00
V2	interrupts	edn_intr	0.690s	5.495s	28.557us	6	6	100.00
V2	alerts	edn_alert	0.840s	5.349s	264.845us	20	20	100.00
V2	errs	edn_err	0.780s	5.455s	25.990us	8	8	100.00
V2	disable	edn_disable	0.590s	5.324s	14.328us	9	9	100.00
		edn_disable_auto_req_mode	0.840s	5.363s	41.730us	9	9	100.00
V2	stress_all	edn_stress_all	3.520s	7.664s	467.944us	3	3	100.00
V2	intr_test	edn_intr_test	0.610s	4.736s	16.246us	50	50	100.00
V2	alert_test	edn_alert_test	0.820s	5.311s	81.711us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.670s	6.582s	526.312us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.670s	6.582s	526.312us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.630s	4.539s	20.494us	5	5	100.00
		edn_csr_rw	0.610s	4.821s	17.415us	20	20	100.00
		edn_csr_aliasing	0.910s	4.523s	36.921us	5	5	100.00
		edn_same_csr_outstanding	0.800s	4.516s	109.333us	3	3	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.630s	4.539s	20.494us	5	5	100.00
		edn_csr_rw	0.610s	4.821s	17.415us	20	20	100.00
		edn_csr_aliasing	0.910s	4.523s	36.921us	5	5	100.00
		edn_same_csr_outstanding	0.800s	4.516s	109.333us	3	3	100.00
V2		TOTAL				139	139	100.00
V2S	tl_intg_err	edn_sec_cm	2.810s	6.543s	1.077ms	3	3	100.00
		edn_tl_intg_err	1.580s	5.505s	110.318us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.670s	5.541s	17.048us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	0.840s	5.349s	264.845us	20	20	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	2.810s	6.543s	1.077ms	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	2.810s	6.543s	1.077ms	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	2.810s	6.543s	1.077ms	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	2.810s	6.543s	1.077ms	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.840s	5.349s	264.845us	20	20	100.00
		edn_sec_cm	2.810s	6.543s	1.077ms	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.840s	5.349s	264.845us	20	20	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.580s	5.505s	110.318us	3	3	100.00
V2S		TOTAL				16	16	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	38.420s	41.934s	9.815ms	6	6	100.00
V3		TOTAL				6	6	100.00
		TOTAL				217	217	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.79	98.48	94.77	96.15	82.95	94.59	97.14	92.44

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22