ENTROPY_SRC/RNG16BITS Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	0.900s	5.309s	72.955us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	0.870s	4.492s	107.183us	7	7	100.00
V1	csr_rw	entropy_src_csr_rw	0.830s	4.660s	27.778us	20	20	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	6.670s	10.073s	519.684us	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	2.430s	6.702s	66.779us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	1.520s	5.624s	136.240us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	0.830s	4.660s	27.778us	20	20	100.00
		entropy_src_csr_aliasing	2.430s	6.702s	66.779us	5	5	100.00
V1		TOTAL				58	58	100.00
V2	firmware	entropy_src_smoke	0.900s	5.309s	72.955us	1	1	100.00
		entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
		entropy_src_fw_ov	6.458m	6.512m	20.024ms	19	20	95.00
V2	firmware_mode	entropy_src_fw_ov	6.458m	6.512m	20.024ms	19	20	95.00
V2	rng_mode	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	11.345m	11.409m	20.049ms	47	47	100.00
V2	health_checks	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
V2	conditioning	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
V2	interrupts	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
		entropy_src_intr	20.230s	24.252s	953.561us	12	12	100.00
V2	alerts	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
		entropy_src_functional_alerts	3.390s	6.587s	350.171us	3	3	100.00
V2	stress_all	entropy_src_stress_all	7.436m	7.498m	20.132ms	5	5	100.00
V2	functional_errors	entropy_src_functional_errors	0.990s	4.498s	42.109us	129	129	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	2.260s	5.493s	176.463us	3	3	100.00
V2	intr_test	entropy_src_intr_test	0.770s	4.853s	29.806us	50	50	100.00
V2	alert_test	entropy_src_alert_test	0.750s	4.451s	103.198us	3	3	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	3.150s	6.485s	659.232us	5	5	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	3.150s	6.485s	659.232us	5	5	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	0.870s	4.492s	107.183us	7	7	100.00
		entropy_src_csr_rw	0.830s	4.660s	27.778us	20	20	100.00
		entropy_src_csr_aliasing	2.430s	6.702s	66.779us	5	5	100.00
		entropy_src_same_csr_outstanding	1.390s	5.577s	374.564us	3	3	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	0.870s	4.492s	107.183us	7	7	100.00
		entropy_src_csr_rw	0.830s	4.660s	27.778us	20	20	100.00
		entropy_src_csr_aliasing	2.430s	6.702s	66.779us	5	5	100.00
		entropy_src_same_csr_outstanding	1.390s	5.577s	374.564us	3	3	100.00
V2		TOTAL				329	330	99.70
V2S	tl_intg_err	entropy_src_sec_cm	1.130s	4.394s	282.986us	3	3	100.00
		entropy_src_tl_intg_err	3.160s	6.785s	4.428ms	16	16	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
		entropy_src_cfg_regwen	0.800s	4.402s	22.337us	3	3	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
V2S	sec_cm_config_redun	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
		entropy_src_fw_ov	6.458m	6.512m	20.024ms	19	20	95.00
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	0.990s	4.498s	42.109us	129	129	100.00
		entropy_src_sec_cm	1.130s	4.394s	282.986us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	0.990s	4.498s	42.109us	129	129	100.00
		entropy_src_sec_cm	1.130s	4.394s	282.986us	3	3	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	5.891m	5.952m	18.063ms	50	50	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	0.990s	4.498s	42.109us	129	129	100.00
		entropy_src_sec_cm	1.130s	4.394s	282.986us	3	3	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	0.990s	4.498s	42.109us	129	129	100.00
		entropy_src_sec_cm	1.130s	4.394s	282.986us	3	3	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	0.990s	4.498s	42.109us	129	129	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	3.390s	6.587s	350.171us	3	3	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	3.160s	6.785s	4.428ms	16	16	100.00
V2S		TOTAL				22	22	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	5.026m	5.087m	15.027ms	8	8	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset				0	0	--
V3		TOTAL				8	8	100.00
		TOTAL				417	418	99.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.52	97.56	90.00	77.39	62.07	95.55	89.43	93.63

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly has 1 failures:
  • Test entropy_src_fw_ov has 1 failures.

    • 18.entropy_src_fw_ov.5042449621288432146348463138454342219297081784054765825788339689792622382814
      Line 849, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/entropy_src_rng16bits-sim-vcs/18.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 10844053923 ps: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_alert triggered unexpectedly
        UVM_INFO @ 10844053923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---