ENTROPY_SRC/RNG4BITS Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	0.780s	4.962s	72.621us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	0.810s	4.958s	25.060us	3	3	100.00
V1	csr_rw	entropy_src_csr_rw	0.770s	5.055s	55.166us	20	20	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	6.750s	9.920s	2.939ms	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	2.730s	6.149s	804.731us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	1.290s	5.204s	60.326us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	0.770s	5.055s	55.166us	20	20	100.00
		entropy_src_csr_aliasing	2.730s	6.149s	804.731us	5	5	100.00
V1		TOTAL				54	54	100.00
V2	firmware	entropy_src_smoke	0.780s	4.962s	72.621us	1	1	100.00
		entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
		entropy_src_fw_ov	4.822m	4.890m	19.066ms	18	19	94.74
V2	firmware_mode	entropy_src_fw_ov	4.822m	4.890m	19.066ms	18	19	94.74
V2	rng_mode	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	10.556m	10.625m	19.049ms	59	59	100.00
V2	health_checks	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
V2	conditioning	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
V2	interrupts	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
		entropy_src_intr	16.810s	20.523s	1.955ms	9	9	100.00
V2	alerts	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
		entropy_src_functional_alerts	2.540s	7.431s	732.975us	3	3	100.00
V2	stress_all	entropy_src_stress_all	5.136m	5.199m	20.283ms	7	7	100.00
V2	functional_errors	entropy_src_functional_errors	0.930s	13.094s	49.529us	46	46	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	1.350s	5.552s	35.450us	3	3	100.00
V2	intr_test	entropy_src_intr_test	0.710s	5.033s	101.995us	50	50	100.00
V2	alert_test	entropy_src_alert_test	0.690s	4.682s	24.030us	3	3	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	2.050s	6.554s	100.066us	5	5	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	2.050s	6.554s	100.066us	5	5	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	0.810s	4.958s	25.060us	3	3	100.00
		entropy_src_csr_rw	0.770s	5.055s	55.166us	20	20	100.00
		entropy_src_csr_aliasing	2.730s	6.149s	804.731us	5	5	100.00
		entropy_src_same_csr_outstanding	0.930s	4.896s	209.937us	3	3	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	0.810s	4.958s	25.060us	3	3	100.00
		entropy_src_csr_rw	0.770s	5.055s	55.166us	20	20	100.00
		entropy_src_csr_aliasing	2.730s	6.149s	804.731us	5	5	100.00
		entropy_src_same_csr_outstanding	0.930s	4.896s	209.937us	3	3	100.00
V2		TOTAL				242	243	99.59
V2S	tl_intg_err	entropy_src_sec_cm	1.100s	4.692s	470.004us	3	3	100.00
		entropy_src_tl_intg_err	2.330s	6.218s	275.960us	13	13	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
		entropy_src_cfg_regwen	0.770s	4.704s	20.110us	4	4	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
V2S	sec_cm_config_redun	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
		entropy_src_fw_ov	4.822m	4.890m	19.066ms	18	19	94.74
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	0.930s	13.094s	49.529us	46	46	100.00
		entropy_src_sec_cm	1.100s	4.692s	470.004us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	0.930s	13.094s	49.529us	46	46	100.00
		entropy_src_sec_cm	1.100s	4.692s	470.004us	3	3	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	5.532m	5.584m	19.020ms	36	36	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	0.930s	13.094s	49.529us	46	46	100.00
		entropy_src_sec_cm	1.100s	4.692s	470.004us	3	3	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	0.930s	13.094s	49.529us	46	46	100.00
		entropy_src_sec_cm	1.100s	4.692s	470.004us	3	3	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	0.930s	13.094s	49.529us	46	46	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	2.540s	7.431s	732.975us	3	3	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	2.330s	6.218s	275.960us	13	13	100.00
V2S		TOTAL				20	20	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	4.773m	4.824m	19.023ms	14	14	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset				0	0	--
V3		TOTAL				14	14	100.00
		TOTAL				330	331	99.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.62	97.02	91.96	75.41	62.07	94.55	89.36	95.97

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 1 failures:
  • Test entropy_src_fw_ov has 1 failures.

    • 18.entropy_src_fw_ov.114018389550532510531105056785196326642621915839914431784278642032053787937185
      Line 1361, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/entropy_src_rng4bits-sim-vcs/18.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 17947412770 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 17947412770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---