2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 1.197m | 1.262m | 36.851us | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 9.760s | 13.255s | 20.556us | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 17.360s | 21.384s | 54.756us | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 45.840s | 50.048s | 3.417ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 42.090s | 46.205s | 11.241ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 8.840s | 12.686s | 178.851us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 42.090s | 46.205s | 11.241ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 4.970s | 8.563s | 56.136us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 5.110s | 9.704s | 18.117us | 5 | 5 | 100.00 |
| V1 | TOTAL | 120 | 120 | 100.00 | ||||
| V2 | sw_op | flash_ctrl_sw_op | 9.990s | 13.200s | 22.407us | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 26.830s | 30.283s | 280.442us | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 23.037m | 23.091m | 1.152s | 3 | 3 | 100.00 |
| flash_ctrl_hw_rma_reset | 8.444m | 8.501m | 80.140ms | 3 | 3 | 100.00 | ||
| flash_ctrl_lcmgr_intg | 5.030s | 8.264s | 93.574us | 4 | 4 | 100.00 | ||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 27.308m | 27.389m | 272.827ms | 6 | 6 | 100.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 2.690m | 2.749m | 6.312ms | 3 | 3 | 100.00 |
| V2 | program_reset | flash_ctrl_prog_reset | 2.110m | 2.171m | 2.705ms | 30 | 30 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 24.968m | 25.041m | 78.241ms | 3 | 3 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 43.850s | 47.392s | 3.073ms | 3 | 3 | 100.00 |
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 13.190s | 17.068s | 186.205us | 3 | 4 | 75.00 |
| flash_ctrl_rw_evict_all_en | 12.590s | 16.280s | 44.429us | 5 | 5 | 100.00 | ||
| flash_ctrl_re_evict | 14.860s | 18.392s | 143.041us | 5 | 5 | 100.00 | ||
| V2 | host_arb | flash_ctrl_phy_arb | 2.495m | 2.548m | 752.691us | 3 | 3 | 100.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 2.495m | 2.548m | 752.691us | 3 | 3 | 100.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 5.677m | 5.741m | 27.530ms | 4 | 4 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 11.260s | 15.221s | 1.046ms | 4 | 4 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 6.770m | 6.835m | 198.324us | 20 | 20 | 100.00 |
| V2 | error_mp | flash_ctrl_error_mp | 7.954m | 8.015m | 10.285ms | 3 | 3 | 100.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 4.733m | 4.794m | 1.162ms | 3 | 3 | 100.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 13.789m | 13.849m | 1.721ms | 3 | 3 | 100.00 |
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 5.000s | 8.269s | 38.916us | 4 | 4 | 100.00 |
| V2 | read_write_overflow | flash_ctrl_oversize_error | 1.841m | 1.898m | 4.416ms | 3 | 3 | 100.00 |
| V2 | flash_ctrl_disable | flash_ctrl_disable | 8.700s | 12.296s | 72.672us | 10 | 10 | 100.00 |
| V2 | flash_ctrl_connect | flash_ctrl_connect | 6.140s | 9.063s | 8.428us | 0 | 3 | 0.00 |
| V2 | stress_all | flash_ctrl_stress_all | 9.352m | 9.414m | 5.188ms | 5 | 5 | 100.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 1.920m | 1.977m | 2.478ms | 4 | 4 | 100.00 |
| flash_ctrl_otp_reset | 49.130s | 53.154s | 88.301us | 6 | 6 | 100.00 | ||
| V2 | isolation_partition | flash_ctrl_hw_rma | 23.037m | 23.091m | 1.152s | 3 | 3 | 100.00 |
| V2 | interrupts | flash_ctrl_intr_rd | 2.411m | 2.469m | 3.703ms | 6 | 6 | 100.00 |
| flash_ctrl_intr_wr | 55.110s | 59.124s | 11.238ms | 10 | 10 | 100.00 | ||
| flash_ctrl_intr_rd_slow_flash | 2.643m | 2.696m | 47.709ms | 5 | 5 | 100.00 | ||
| flash_ctrl_intr_wr_slow_flash | 3.336m | 3.399m | 125.931ms | 3 | 3 | 100.00 | ||
| V2 | invalid_op | flash_ctrl_invalid_op | 48.570s | 52.348s | 15.989ms | 3 | 3 | 100.00 |
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 32.810s | 36.554s | 1.298ms | 3 | 3 | 100.00 |
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 9.050s | 13.147s | 26.500us | 5 | 5 | 100.00 |
| flash_ctrl_ro_derr | 1.535m | 1.595m | 5.327ms | 10 | 10 | 100.00 | ||
| flash_ctrl_rw_derr | 2.508m | 2.566m | 1.853ms | 3 | 3 | 100.00 | ||
| flash_ctrl_derr_detect | 1.669m | 1.726m | 1.760ms | 5 | 5 | 100.00 | ||
| flash_ctrl_integrity | 7.476m | 7.534m | 15.682ms | 5 | 5 | 100.00 | ||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 9.270s | 13.125s | 30.846us | 5 | 5 | 100.00 |
| flash_ctrl_ro_serr | 1.419m | 1.473m | 553.217us | 3 | 3 | 100.00 | ||
| flash_ctrl_rw_serr | 2.281m | 2.339m | 32.820ms | 3 | 3 | 100.00 | ||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 53.260s | 56.570s | 897.066us | 5 | 5 | 100.00 |
| V2 | singlebit_err_address | flash_ctrl_serr_address | 56.550s | 59.686s | 4.510ms | 5 | 5 | 100.00 |
| V2 | scramble | flash_ctrl_wo | 2.800m | 2.859m | 26.658ms | 20 | 20 | 100.00 |
| flash_ctrl_write_word_sweep | 6.130s | 9.255s | 40.601us | 1 | 1 | 100.00 | ||
| flash_ctrl_read_word_sweep | 5.570s | 9.216s | 73.059us | 1 | 1 | 100.00 | ||
| flash_ctrl_ro | 1.198m | 1.258m | 728.432us | 18 | 20 | 90.00 | ||
| flash_ctrl_rw | 6.664m | 6.725m | 4.563ms | 4 | 4 | 100.00 | ||
| V2 | filesystem_support | flash_ctrl_fs_sup | 20.730s | 24.554s | 1.566ms | 3 | 3 | 100.00 |
| V2 | rma_write_process_error | flash_ctrl_rma_err | 10.187m | 10.249m | 165.758ms | 3 | 3 | 100.00 |
| flash_ctrl_hw_prog_rma_wipe_err | 1.727m | 1.793m | 10.033ms | 5 | 5 | 100.00 | ||
| V2 | alert_test | flash_ctrl_alert_test | 5.280s | 9.201s | 131.716us | 3 | 3 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 4.970s | 9.332s | 16.838us | 5 | 5 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 10.070s | 15.261s | 621.000us | 5 | 5 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 10.070s | 15.261s | 621.000us | 5 | 5 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 17.360s | 21.384s | 54.756us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 42.090s | 46.205s | 11.241ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 15.830s | 20.175s | 1.636ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 17.360s | 21.384s | 54.756us | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 42.090s | 46.205s | 11.241ms | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 15.830s | 20.175s | 1.636ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 317 | 323 | 98.14 | ||||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 47.610s | 51.557s | 444.891us | 3 | 3 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| flash_ctrl_tl_intg_err | 17.770s | 22.075s | 64.360us | 0 | 12 | 0.00 | ||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 17.770s | 22.075s | 64.360us | 0 | 12 | 0.00 |
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 17.770s | 22.075s | 64.360us | 0 | 12 | 0.00 |
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 13.130s | 16.371s | 232.543us | 3 | 3 | 100.00 |
| flash_ctrl_wr_intg | 5.970s | 9.252s | 47.665us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 1.197m | 1.262m | 36.851us | 50 | 50 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 49.130s | 53.154s | 88.301us | 6 | 6 | 100.00 |
| flash_ctrl_disable | 8.700s | 12.296s | 72.672us | 10 | 10 | 100.00 | ||
| flash_ctrl_sec_info_access | 39.980s | 43.156s | 4.244ms | 11 | 11 | 100.00 | ||
| flash_ctrl_connect | 6.140s | 9.063s | 8.428us | 0 | 3 | 0.00 | ||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 5.240s | 8.283s | 39.660us | 3 | 3 | 100.00 |
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 |
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 |
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 7.230s | 11.835s | 255.644us | 20 | 20 | 100.00 |
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 33.410s | 37.596s | 43.120us | 4 | 4 | 100.00 |
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 8.700s | 12.296s | 72.672us | 10 | 10 | 100.00 |
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 13.130s | 16.371s | 232.543us | 3 | 3 | 100.00 |
| flash_ctrl_access_after_disable | 5.250s | 9.211s | 208.702us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_mem_addr_infection | flash_ctrl_host_addr_infection | 12.130s | 15.344s | 36.414us | 3 | 3 | 100.00 |
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 8.700s | 12.296s | 72.672us | 10 | 10 | 100.00 |
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 11.260s | 15.221s | 1.046ms | 4 | 4 | 100.00 |
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 6.664m | 6.725m | 4.563ms | 4 | 4 | 100.00 |
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 2.281m | 2.339m | 32.820ms | 3 | 3 | 100.00 |
| flash_ctrl_rw_derr | 2.508m | 2.566m | 1.853ms | 3 | 3 | 100.00 | ||
| flash_ctrl_integrity | 7.476m | 7.534m | 15.682ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 23.037m | 23.091m | 1.152s | 3 | 3 | 100.00 |
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 10.370s | 14.351s | 863.687us | 10 | 10 | 100.00 |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 5.370s | 9.249s | 24.828us | 3 | 3 | 100.00 |
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 5.330s | 9.239s | 130.954us | 4 | 5 | 80.00 |
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 1.126m | 1.192m | 259.526us | 0 | 4 | 0.00 |
| V2S | TOTAL | 54 | 71 | 76.06 | ||||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 17.700s | 21.485s | 57.788us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | |||
| V3 | TOTAL | 1 | 1 | 100.00 | ||||
| Unmapped tests | flash_ctrl_basic_rw | 3.860m | 3.914m | 1.406ms | 3 | 3 | 100.00 | |
| TOTAL | 495 | 518 | 95.56 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 55 | 55 | 52 | 94.55 |
| V2S | 13 | 13 | 10 | 76.92 |
| V3 | 2 | 1 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 94.30 | 95.48 | 94.24 | 95.39 | 87.18 | 96.69 | 94.33 | 96.78 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: * has 10 failures:
Test flash_ctrl_sec_cm has 2 failures.
1.flash_ctrl_sec_cm.87008641775805735644356048678575346968059813615969605980964257647384372198689
Line 172, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 67422.8 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
UVM_INFO @ 67422.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.flash_ctrl_sec_cm.23628916549527844161538548098128259513486109190356844216913579663746268114462
Line 480, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 140837.2 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
UVM_INFO @ 140837.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_tl_intg_err has 8 failures.
1.flash_ctrl_tl_intg_err.104439143616355003910054630689837909878417849644520584028893029908809983273366
Line 148, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_tl_intg_err/latest/run.log
UVM_ERROR @ 513209.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
UVM_INFO @ 513209.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.flash_ctrl_tl_intg_err.15421792800236101649709375934649609770694545992676133033944763053062557345326
Line 151, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_tl_intg_err/latest/run.log
UVM_ERROR @ 29398.4 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
UVM_INFO @ 29398.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [flash_ctrl_common_vseq] expect alert:fatal_std_err to fire has 6 failures:
Test flash_ctrl_sec_cm has 2 failures.
0.flash_ctrl_sec_cm.25890058853724864813583478369669609416817011296116201383534424779715785794381
Line 160, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 13077.1 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
UVM_INFO @ 13077.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.flash_ctrl_sec_cm.16117669529758447124951411575179758217084960259472831180325909703863308176352
Line 586, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log
UVM_ERROR @ 259526.0 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
UVM_INFO @ 259526.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test flash_ctrl_tl_intg_err has 4 failures.
0.flash_ctrl_tl_intg_err.34955554058821761213738752080173247492715965552523346542866084723739923873413
Line 154, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_tl_intg_err/latest/run.log
UVM_ERROR @ 172109.1 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
UVM_INFO @ 172109.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.flash_ctrl_tl_intg_err.17517869752019953717481187230566666547130256373573307639557353528887417430400
Line 147, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/6.flash_ctrl_tl_intg_err/latest/run.log
UVM_ERROR @ 39321.9 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
UVM_INFO @ 39321.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i) has 3 failures:
0.flash_ctrl_connect.35627080038149074901853943854922531500011494900334294881257839376310814041454
Line 114, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_connect/latest/run.log
UVM_ERROR @ 12602.1 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_INFO @ 12602.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_connect.33924167945099380775365254856062963439568301884847960454339677043433402133636
Line 114, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_connect/latest/run.log
UVM_ERROR @ 8176.3 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_INFO @ 8176.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
2.flash_ctrl_rw_evict.78181466680665939929945645405779256478200050786853359943675311296687516820557
Line 114, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log
UVM_ERROR @ 11798.0 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
UVM_INFO @ 11798.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
3.flash_ctrl_phy_ack_consistency.37199836781658851233641539998199384963333944034116739938851949066830198808721
Line 122, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest/run.log
UVM_ERROR @ 9329.9 ns: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x3)
UVM_INFO @ 9329.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
10.flash_ctrl_ro.4039127699948811722283424235250219674583213559701923246654831228965300501061
Line 114, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/10.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 1519816.5 ns: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
UVM_INFO @ 1519816.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
14.flash_ctrl_ro.21598271763569987933484561280290168117718149784956787977240354876677364686209
Line 114, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/flash_ctrl_top_egret-sim-vcs/14.flash_ctrl_ro/latest/run.log
UVM_ERROR @ 361197.3 ns: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
UVM_INFO @ 361197.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---