2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | smoke | gpio_smoke | 0.670s | 4.528s | 86.190us | 1 | 1 | 100.00 |
| gpio_smoke_no_pullup_pulldown | 0.650s | 4.504s | 26.374us | 1 | 1 | 100.00 | ||
| gpio_smoke_en_cdc_prim | 0.690s | 4.649s | 47.293us | 1 | 1 | 100.00 | ||
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 0.890s | 4.640s | 77.586us | 1 | 1 | 100.00 | ||
| V1 | csr_hw_reset | gpio_csr_hw_reset | 0.540s | 4.630s | 27.082us | 5 | 5 | 100.00 |
| V1 | csr_rw | gpio_csr_rw | 0.590s | 4.476s | 14.726us | 3 | 3 | 100.00 |
| V1 | csr_bit_bash | gpio_csr_bit_bash | 4.060s | 7.780s | 700.340us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | gpio_csr_aliasing | 1.390s | 4.756s | 214.594us | 4 | 5 | 80.00 |
| V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 0.950s | 4.519s | 50.155us | 3 | 3 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.590s | 4.476s | 14.726us | 3 | 3 | 100.00 |
| gpio_csr_aliasing | 1.390s | 4.756s | 214.594us | 4 | 5 | 80.00 | ||
| V1 | TOTAL | 24 | 25 | 96.00 | ||||
| V2 | direct_and_masked_out | gpio_random_dout_din | 0.730s | 4.509s | 68.587us | 1 | 1 | 100.00 |
| gpio_random_dout_din_no_pullup_pulldown | 0.690s | 4.540s | 38.407us | 1 | 1 | 100.00 | ||
| V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 0.620s | 4.532s | 69.705us | 3 | 3 | 100.00 |
| V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 0.550s | 4.465s | 61.147us | 1 | 1 | 100.00 |
| V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 1.110s | 4.456s | 264.624us | 1 | 1 | 100.00 |
| V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 1.650s | 5.412s | 73.511us | 3 | 3 | 100.00 |
| V2 | noise_filter_stress | gpio_filter_stress | 8.470s | 11.969s | 418.162us | 1 | 1 | 100.00 |
| V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 1.470s | 5.423s | 513.222us | 3 | 3 | 100.00 |
| V2 | full_random | gpio_full_random | 0.510s | 4.326s | 60.572us | 1 | 1 | 100.00 |
| V2 | stress_all | gpio_stress_all | 1.779m | 1.842m | 14.273ms | 3 | 3 | 100.00 |
| V2 | alert_test | gpio_alert_test | 0.460s | 4.289s | 148.033us | 3 | 3 | 100.00 |
| V2 | intr_test | gpio_intr_test | 0.540s | 4.723s | 19.473us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | gpio_tl_errors | 1.760s | 5.375s | 1.736ms | 3 | 3 | 100.00 |
| V2 | tl_d_illegal_access | gpio_tl_errors | 1.760s | 5.375s | 1.736ms | 3 | 3 | 100.00 |
| V2 | tl_d_outstanding_access | gpio_csr_rw | 0.590s | 4.476s | 14.726us | 3 | 3 | 100.00 |
| gpio_same_csr_outstanding | 0.880s | 5.319s | 30.355us | 15 | 20 | 75.00 | ||
| gpio_csr_aliasing | 1.390s | 4.756s | 214.594us | 4 | 5 | 80.00 | ||
| gpio_csr_hw_reset | 0.540s | 4.630s | 27.082us | 5 | 5 | 100.00 | ||
| V2 | tl_d_partial_access | gpio_csr_rw | 0.590s | 4.476s | 14.726us | 3 | 3 | 100.00 |
| gpio_same_csr_outstanding | 0.880s | 5.319s | 30.355us | 15 | 20 | 75.00 | ||
| gpio_csr_aliasing | 1.390s | 4.756s | 214.594us | 4 | 5 | 80.00 | ||
| gpio_csr_hw_reset | 0.540s | 4.630s | 27.082us | 5 | 5 | 100.00 | ||
| V2 | TOTAL | 89 | 94 | 94.68 | ||||
| V2S | tl_intg_err | gpio_tl_intg_err | 1.930s | 5.761s | 2.386ms | 12 | 12 | 100.00 |
| gpio_sec_cm | 0.720s | 4.301s | 165.833us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.930s | 5.761s | 2.386ms | 12 | 12 | 100.00 |
| V2S | TOTAL | 15 | 15 | 100.00 | ||||
| V3 | straps_data | gpio_rand_straps | 0.410s | 4.342s | 33.743us | 1 | 1 | 100.00 |
| V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 0.520s | 4.302s | 99.333us | 0 | 1 | 0.00 |
| V3 | TOTAL | 1 | 2 | 50.00 | ||||
| Unmapped tests | gpio_inp_prd_cnt | 0.510s | 4.504s | 44.436us | 12 | 12 | 100.00 | |
| TOTAL | 141 | 148 | 95.27 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 9 | 9 | 8 | 88.89 |
| V2 | 14 | 14 | 13 | 92.86 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.39 | 99.89 | 95.76 | 80.88 | 75.00 | 98.38 | 96.84 | 100.00 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_ERROR (cip_base_vseq.sv:649) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 5 failures:
3.gpio_same_csr_outstanding.34042613519901529451375051290204978604609654188652795605067100193383788109787
Line 79, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/gpio_top_dragonfly-sim-vcs/3.gpio_same_csr_outstanding/latest/run.log
UVM_ERROR @ 65283233 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (2 [0x2] vs 0 [0x0]) addr 0x7115267c read out mismatch
UVM_INFO @ 65283233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.gpio_same_csr_outstanding.98834621824513953768020346679528181457600507673641757826449403305444793321462
Line 79, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/gpio_top_dragonfly-sim-vcs/4.gpio_same_csr_outstanding/latest/run.log
UVM_ERROR @ 19403203 ps: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed masked_data == exp_data (1 [0x1] vs 0 [0x0]) addr 0x73a35774 read out mismatch
UVM_INFO @ 19403203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (cip_base_vseq.sv:1171) [gpio_common_vseq] Check failed (vseq_done) has 1 failures:
0.gpio_stress_all_with_rand_reset.83821585686173722915748682612889387158843779104487561200910081104843635740570
Line 82, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/gpio_top_dragonfly-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 99332794 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
UVM_INFO @ 99332794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * has 1 failures:
1.gpio_csr_aliasing.10452451723024133593929287451227820508579459855957863539666800477280480883279
Line 80, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/gpio_top_dragonfly-sim-vcs/1.gpio_csr_aliasing/latest/run.log
UVM_ERROR @ 214594475 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (28 [0x1c] vs 0 [0x0]) Regname: gpio_reg_block.inp_prd_cnt_val_2 reset value: 0x0
UVM_INFO @ 214594475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---