GPIO/EGRET Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	0.900s	5.484s	64.478us	1	1	100.00
		gpio_smoke_no_pullup_pulldown	0.860s	5.456s	169.459us	1	1	100.00
		gpio_smoke_en_cdc_prim	0.650s	4.539s	35.427us	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.070s	4.546s	390.340us	1	1	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.490s	4.412s	32.885us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.470s	4.530s	38.869us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.250s	5.421s	739.401us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.580s	4.326s	28.573us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	0.640s	4.315s	110.953us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.470s	4.530s	38.869us	20	20	100.00
		gpio_csr_aliasing	0.580s	4.326s	28.573us	5	5	100.00
V1		TOTAL				42	42	100.00
V2	direct_and_masked_out	gpio_random_dout_din	0.720s	5.404s	23.329us	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	0.790s	4.317s	62.598us	1	1	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.580s	4.309s	247.868us	1	1	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	0.910s	4.300s	434.798us	1	1	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	2.070s	6.432s	115.916us	1	1	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	2.270s	6.424s	88.026us	3	3	100.00
V2	noise_filter_stress	gpio_filter_stress	6.930s	11.691s	1.501ms	1	1	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	1.990s	6.400s	778.511us	1	1	100.00
V2	full_random	gpio_full_random	0.650s	4.322s	736.562us	1	1	100.00
V2	stress_all	gpio_stress_all	1.318m	1.381m	10.371ms	4	4	100.00
V2	alert_test	gpio_alert_test	0.450s	5.250s	14.576us	3	3	100.00
V2	intr_test	gpio_intr_test	0.470s	4.607s	31.018us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	1.680s	5.407s	119.295us	4	4	100.00
V2	tl_d_illegal_access	gpio_tl_errors	1.680s	5.407s	119.295us	4	4	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.470s	4.530s	38.869us	20	20	100.00
		gpio_same_csr_outstanding	0.640s	4.330s	17.979us	3	3	100.00
		gpio_csr_aliasing	0.580s	4.326s	28.573us	5	5	100.00
		gpio_csr_hw_reset	0.490s	4.412s	32.885us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.470s	4.530s	38.869us	20	20	100.00
		gpio_same_csr_outstanding	0.640s	4.330s	17.979us	3	3	100.00
		gpio_csr_aliasing	0.580s	4.326s	28.573us	5	5	100.00
		gpio_csr_hw_reset	0.490s	4.412s	32.885us	5	5	100.00
V2		TOTAL				75	75	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.090s	4.418s	477.026us	7	7	100.00
		gpio_sec_cm	0.620s	5.256s	150.034us	3	3	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.090s	4.418s	477.026us	7	7	100.00
V2S		TOTAL				10	10	100.00
V3	straps_data	gpio_rand_straps	0.450s	4.255s	12.697us	1	1	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	6.240s	9.594s	572.082us	0	1	0.00
V3		TOTAL				1	2	50.00
		TOTAL				128	129	99.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.08	99.76	99.57	80.52	--	99.80	96.84	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:1171) [gpio_common_vseq] Check failed (vseq_done) has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.110632702183567970399677137292278570218717021097739300012263532019348930440873
      Line 238, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/gpio_top_egret-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 572081965 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 572081965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---