HMAC Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.640s	11.495s	3.637ms	1	1	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.720s	4.444s	74.517us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.620s	4.426s	97.032us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	10.640s	14.003s	2.194ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	4.090s	7.561s	1.591ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	7.542m	7.597m	394.522ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.620s	4.426s	97.032us	20	20	100.00
		hmac_csr_aliasing	4.090s	7.561s	1.591ms	5	5	100.00
V1		TOTAL				56	56	100.00
V2	long_msg	hmac_long_msg	20.420s	24.180s	8.925ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	55.230s	58.760s	1.209ms	4	4	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.121m	3.212m	9.312ms	8	8	100.00
		hmac_test_sha384_vectors	6.376m	6.488m	16.968ms	17	17	100.00
		hmac_test_sha512_vectors	6.246m	6.367m	22.686ms	19	19	100.00
		hmac_test_hmac256_vectors	9.000s	12.533s	2.562ms	13	13	100.00
		hmac_test_hmac384_vectors	12.780s	16.543s	2.348ms	20	20	100.00
		hmac_test_hmac512_vectors	13.020s	16.781s	462.078us	22	22	100.00
V2	burst_wr	hmac_burst_wr	25.290s	28.520s	3.704ms	4	4	100.00
V2	datapath_stress	hmac_datapath_stress	1.605m	1.665m	1.879ms	1	1	100.00
V2	error	hmac_error	39.440s	43.035s	13.874ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	20.170s	23.972s	3.070ms	1	1	100.00
V2	save_and_restore	hmac_smoke	7.640s	11.495s	3.637ms	1	1	100.00
		hmac_long_msg	20.420s	24.180s	8.925ms	1	1	100.00
		hmac_back_pressure	55.230s	58.760s	1.209ms	4	4	100.00
		hmac_datapath_stress	1.605m	1.665m	1.879ms	1	1	100.00
		hmac_burst_wr	25.290s	28.520s	3.704ms	4	4	100.00
		hmac_stress_all	14.998m	15.102m	43.106ms	7	7	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	7.640s	11.495s	3.637ms	1	1	100.00
		hmac_long_msg	20.420s	24.180s	8.925ms	1	1	100.00
		hmac_back_pressure	55.230s	58.760s	1.209ms	4	4	100.00
		hmac_datapath_stress	1.605m	1.665m	1.879ms	1	1	100.00
		hmac_wipe_secret	20.170s	23.972s	3.070ms	1	1	100.00
		hmac_test_sha256_vectors	3.121m	3.212m	9.312ms	8	8	100.00
		hmac_test_sha384_vectors	6.376m	6.488m	16.968ms	17	17	100.00
		hmac_test_sha512_vectors	6.246m	6.367m	22.686ms	19	19	100.00
		hmac_test_hmac256_vectors	9.000s	12.533s	2.562ms	13	13	100.00
		hmac_test_hmac384_vectors	12.780s	16.543s	2.348ms	20	20	100.00
		hmac_test_hmac512_vectors	13.020s	16.781s	462.078us	22	22	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	7.640s	11.495s	3.637ms	1	1	100.00
		hmac_long_msg	20.420s	24.180s	8.925ms	1	1	100.00
		hmac_back_pressure	55.230s	58.760s	1.209ms	4	4	100.00
		hmac_datapath_stress	1.605m	1.665m	1.879ms	1	1	100.00
		hmac_burst_wr	25.290s	28.520s	3.704ms	4	4	100.00
		hmac_error	39.440s	43.035s	13.874ms	1	1	100.00
		hmac_wipe_secret	20.170s	23.972s	3.070ms	1	1	100.00
		hmac_test_sha256_vectors	3.121m	3.212m	9.312ms	8	8	100.00
		hmac_test_sha384_vectors	6.376m	6.488m	16.968ms	17	17	100.00
		hmac_test_sha512_vectors	6.246m	6.367m	22.686ms	19	19	100.00
		hmac_test_hmac256_vectors	9.000s	12.533s	2.562ms	13	13	100.00
		hmac_test_hmac384_vectors	12.780s	16.543s	2.348ms	20	20	100.00
		hmac_test_hmac512_vectors	13.020s	16.781s	462.078us	22	22	100.00
		hmac_stress_all	14.998m	15.102m	43.106ms	7	7	100.00
V2	stress_all	hmac_stress_all	14.998m	15.102m	43.106ms	7	7	100.00
V2	alert_test	hmac_alert_test	0.420s	5.705s	23.065us	3	3	100.00
V2	intr_test	hmac_intr_test	0.480s	4.439s	12.646us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	2.980s	6.487s	88.676us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	2.980s	6.487s	88.676us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.720s	4.444s	74.517us	5	5	100.00
		hmac_csr_rw	0.620s	4.426s	97.032us	20	20	100.00
		hmac_csr_aliasing	4.090s	7.561s	1.591ms	5	5	100.00
		hmac_same_csr_outstanding	1.730s	5.470s	1.340ms	3	3	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.720s	4.444s	74.517us	5	5	100.00
		hmac_csr_rw	0.620s	4.426s	97.032us	20	20	100.00
		hmac_csr_aliasing	4.090s	7.561s	1.591ms	5	5	100.00
		hmac_same_csr_outstanding	1.730s	5.470s	1.340ms	3	3	100.00
V2		TOTAL				194	194	100.00
V2S	tl_intg_err	hmac_sec_cm	0.760s	5.720s	98.765us	3	3	100.00
		hmac_tl_intg_err	2.960s	6.416s	536.319us	4	4	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.960s	6.416s	536.319us	4	4	100.00
V2S		TOTAL				7	7	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.640s	11.495s	3.637ms	1	1	100.00
V3	stress_reset	hmac_stress_reset	2.360s	6.058s	157.530us	3	3	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	5.325m	5.435m	6.730ms	9	9	100.00
V3		TOTAL				12	12	100.00
	Unmapped tests	hmac_directed	2.360s	6.206s	771.249us	4	4	100.00
		TOTAL				273	273	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.41	99.74	96.45	100.00	97.14	97.75	97.80	100.00

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22