2aab100d17| Stage | Name | Tests | Max Job Runtime | Max Wall Clock | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 39.210s | 42.968s | 1.264ms | 3 | 3 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 13.290s | 16.328s | 5.439ms | 4 | 4 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.560s | 5.294s | 19.742us | 5 | 5 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.570s | 5.284s | 85.288us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.270s | 6.882s | 1.868ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.300s | 4.563s | 456.900us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 1.030s | 4.726s | 34.618us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.570s | 5.284s | 85.288us | 20 | 20 | 100.00 |
| i2c_csr_aliasing | 1.300s | 4.563s | 456.900us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 62 | 62 | 100.00 | ||||
| V2 | host_error_intr | i2c_host_error_intr | 1.300s | 4.440s | 658.536us | 2 | 5 | 40.00 |
| V2 | host_stress_all | i2c_host_stress_all | 18.917m | 18.985m | 16.650ms | 4 | 7 | 57.14 |
| V2 | host_maxperf | i2c_host_perf | 5.830m | 5.899m | 12.281ms | 5 | 5 | 100.00 |
| V2 | host_override | i2c_host_override | 0.500s | 4.449s | 48.170us | 5 | 5 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 2.723m | 2.782m | 16.083ms | 4 | 4 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 1.608m | 1.660m | 2.978ms | 3 | 3 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 0.760s | 4.412s | 421.768us | 5 | 5 | 100.00 |
| i2c_host_fifo_fmt_empty | 3.170s | 6.815s | 4.808ms | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 5.350s | 8.602s | 162.685us | 3 | 3 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 1.221m | 1.287m | 3.275ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 21.570s | 25.141s | 5.381ms | 1 | 1 | 100.00 |
| V2 | host_rx_oversample | host_rx_oversample | 0 | 0 | -- | |||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 1.860s | 5.297s | 158.658us | 3 | 4 | 75.00 |
| V2 | target_glitch | i2c_target_glitch | 1.670s | 5.431s | 1.997ms | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 1.974m | 2.028m | 21.630ms | 3 | 3 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 2.990s | 6.477s | 1.113ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 38.600s | 41.836s | 1.336ms | 3 | 3 | 100.00 |
| i2c_target_intr_smoke | 3.130s | 6.531s | 944.478us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.070s | 4.321s | 460.951us | 4 | 4 | 100.00 |
| i2c_target_fifo_reset_tx | 0.710s | 4.276s | 585.389us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 27.590s | 30.650s | 54.700ms | 3 | 3 | 100.00 |
| i2c_target_stress_rd | 38.600s | 41.836s | 1.336ms | 3 | 3 | 100.00 | ||
| i2c_target_intr_stress_wr | 20.930s | 24.151s | 46.058ms | 3 | 3 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 4.480s | 7.509s | 1.422ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 25.490s | 28.417s | 2.535ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 3.430s | 6.450s | 4.722ms | 3 | 3 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 16.040s | 19.384s | 10.015ms | 2 | 3 | 66.67 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 1.390s | 5.371s | 3.985ms | 3 | 3 | 100.00 |
| i2c_target_fifo_watermarks_tx | 0.760s | 4.338s | 131.841us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 5.830m | 5.899m | 12.281ms | 5 | 5 | 100.00 |
| i2c_host_perf_precise | 17.860s | 21.100s | 689.589us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 21.570s | 25.141s | 5.381ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.810s | 6.750s | 437.479us | 3 | 3 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.730s | 5.707s | 530.049us | 3 | 3 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.550s | 5.510s | 1.064ms | 4 | 4 | 100.00 | ||
| i2c_target_nack_txstretch | 1.010s | 4.627s | 134.733us | 3 | 3 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 25.830s | 29.014s | 8.772ms | 8 | 8 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | |||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | |||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | |||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | |||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | |||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | |||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | |||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | |||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | |||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | |||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 1.210s | 4.353s | 449.543us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.450s | 4.400s | 25.070us | 3 | 3 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.520s | 5.304s | 15.942us | 5 | 5 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.680s | 5.551s | 131.123us | 4 | 4 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.680s | 5.551s | 131.123us | 4 | 4 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.560s | 5.294s | 19.742us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.570s | 5.284s | 85.288us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.300s | 4.563s | 456.900us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.830s | 4.551s | 59.121us | 4 | 4 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.560s | 5.294s | 19.742us | 5 | 5 | 100.00 |
| i2c_csr_rw | 0.570s | 5.284s | 85.288us | 20 | 20 | 100.00 | ||
| i2c_csr_aliasing | 1.300s | 4.563s | 456.900us | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.830s | 4.551s | 59.121us | 4 | 4 | 100.00 | ||
| V2 | TOTAL | 106 | 116 | 91.38 | ||||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.480s | 5.502s | 460.283us | 7 | 7 | 100.00 |
| i2c_sec_cm | 0.670s | 4.629s | 68.745us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.480s | 5.502s | 460.283us | 7 | 7 | 100.00 |
| V2S | TOTAL | 10 | 10 | 100.00 | ||||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 24.180s | 27.501s | 817.589us | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.020s | 4.278s | 146.423us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 23.400s | 26.791s | 1.941ms | 0 | 10 | 0.00 |
| V3 | target_loopback | 0 | 0 | -- | ||||
| V3 | TOTAL | 0 | 21 | 0.00 | ||||
| TOTAL | 178 | 209 | 85.17 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 33 | 67.35 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 83.98 | 97.25 | 89.29 | 73.65 | 47.62 | 93.83 | 96.41 | 89.85 |
| Target | Elapsed |
|---|---|
| build | 00:06:40 |
| run | 14:15:03 |
| cov_merge | 14:15:15 |
| cov_report | 14:15:22 |
| Total | 14:15:22 |
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
0.i2c_host_stress_all_with_rand_reset.66036205175900857654173620329716826739142549878519000127417860611799628383786
Line 92, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2544911462 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2544911462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.69506877253620339553794483844222554784394025950244167765319201349891977300546
Line 91, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 574170124 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 574170124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
0.i2c_target_stress_all_with_rand_reset.58040734803398043219506042427199357142939150394150339079027783707543813425978
Line 93, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2188068600 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2188068600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_stress_all_with_rand_reset.61507303568797502719418898211777787460097761721856853187408169811837739386651
Line 86, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 466467678 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 466467678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 6 failures:
Test i2c_host_error_intr has 3 failures.
2.i2c_host_error_intr.102558896093491543000202955319053102267784471628938972474542630753734748701183
Line 88, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/2.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 9262026 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 9262026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_error_intr.19491277025986088648429757127162453560692932485865857869233321040336664365550
Line 88, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/3.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 17998587 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 17998587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_host_stress_all has 2 failures.
4.i2c_host_stress_all.113346787803545642881727074043863903790933996350874784872281961175365363382546
Line 164, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 143538702600 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 143538702600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_host_stress_all.12599258515854986817075713519357102811571586873453195792495506489355505501189
Line 128, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/6.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 7527013995 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 7527013995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
8.i2c_target_stress_all_with_rand_reset.113378481114744671072125936268101675012965112670564317671094010384028529476489
Line 92, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7037689744 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 7037689744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:
0.i2c_target_glitch.8702223051851224680585612394349890880162367705871269158956778528893721491436
Line 86, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 412326475 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 412326475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.113744501617906771833722705691563810927344144925554078580916169361045780511909
Line 86, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 1997039593 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 1997039593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
2.i2c_target_stress_all_with_rand_reset.48687391143520988039482042823830932252818965280970123591313770178639144211715
Line 92, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 619333820 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 619333820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.i2c_target_stress_all_with_rand_reset.103049292638569248345608162599537528189716999369427975600735016509842674530360
Line 100, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 645721938 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 645721938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:
0.i2c_target_unexp_stop.7814474736559386205520425098028547566457700940391493800149703897674383345289
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 146422674 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 146422674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
1.i2c_target_hrst.59160486519973705530115756434689198782448018995949783229396640542184455642201
Line 81, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10015485764 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10015485764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:
2.i2c_host_mode_toggle.60456905412369336033754777012798816206697356241498019862770144804675008731908
Line 87, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 280086827 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @14115
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
5.i2c_host_stress_all.8208956399446396771277981321723973004572091461913986951127859412028516631187
Line 128, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---