KEYMGR Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.750s	5.424s	183.109us	1	1	100.00
V1	random	keymgr_random	12.530s	16.143s	2.158ms	4	4	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.040s	4.362s	35.402us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.910s	13.611s	2.341ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	5.270s	9.101s	134.869us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.440s	5.230s	56.080us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
		keymgr_csr_aliasing	5.270s	9.101s	134.869us	5	5	100.00
V1		TOTAL				60	60	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.278m	1.341m	14.470ms	21	21	100.00
V2	sideload	keymgr_sideload	18.940s	22.041s	1.394ms	3	3	100.00
		keymgr_sideload_kmac	3.950s	7.463s	283.100us	1	1	100.00
		keymgr_sideload_aes	2.120s	6.361s	411.536us	3	3	100.00
		keymgr_sideload_acc	16.450s	19.789s	2.610ms	3	3	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	0.860s	4.238s	143.179us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.490s	7.356s	462.425us	8	8	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	3.480s	7.590s	134.273us	12	12	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.160s	8.294s	197.132us	6	6	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	24.900s	28.295s	12.199ms	9	9	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	12.210s	16.134s	2.469ms	5	5	100.00
V2	stress_all	keymgr_stress_all	3.755m	3.822m	146.709ms	21	21	100.00
V2	intr_test	keymgr_intr_test	0.700s	4.836s	27.936us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.520s	5.305s	61.394us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.190s	6.654s	483.090us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.190s	6.654s	483.090us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.040s	4.362s	35.402us	5	5	100.00
		keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
		keymgr_csr_aliasing	5.270s	9.101s	134.869us	5	5	100.00
		keymgr_same_csr_outstanding	3.070s	6.815s	466.054us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.040s	4.362s	35.402us	5	5	100.00
		keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
		keymgr_csr_aliasing	5.270s	9.101s	134.869us	5	5	100.00
		keymgr_same_csr_outstanding	3.070s	6.815s	466.054us	20	20	100.00
V2		TOTAL				186	186	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
		keymgr_tl_intg_err	10.540s	14.613s	520.258us	16	16	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.810s	6.573s	249.894us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.810s	6.573s	249.894us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.810s	6.573s	249.894us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.810s	6.573s	249.894us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	6.740s	9.794s	764.860us	3	3	100.00
V2S	prim_count_check	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.540s	14.613s	520.258us	16	16	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.810s	6.573s	249.894us	3	3	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.278m	1.341m	14.470ms	21	21	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	12.530s	16.143s	2.158ms	4	4	100.00
		keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	12.530s	16.143s	2.158ms	4	4	100.00
		keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	12.530s	16.143s	2.158ms	4	4	100.00
		keymgr_csr_rw	1.040s	5.232s	118.085us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.490s	7.356s	462.425us	8	8	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	24.900s	28.295s	12.199ms	9	9	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	24.900s	28.295s	12.199ms	9	9	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	12.530s	16.143s	2.158ms	4	4	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.010s	5.525s	120.866us	4	4	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	8.500s	11.736s	3.321ms	25	25	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.490s	7.356s	462.425us	8	8	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	8.500s	11.736s	3.321ms	25	25	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	8.500s	11.736s	3.321ms	25	25	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	8.500s	11.736s	3.321ms	25	25	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.800s	14.684s	621.670us	3	3	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	8.500s	11.736s	3.321ms	25	25	100.00
V2S		TOTAL				54	54	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	13.090s	16.173s	1.064ms	10	12	83.33
V3		TOTAL				10	12	83.33
		TOTAL				310	312	99.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	16	100.00
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.59	99.21	98.18	97.77	100.00	99.01	97.72	91.21

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
  • Test keymgr_stress_all_with_rand_reset has 2 failures.

    • 10.keymgr_stress_all_with_rand_reset.36397079881134272546593101021956799032993578285415188421246159816231044775217
      Line 962, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1104828355 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1104828355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.keymgr_stress_all_with_rand_reset.27265792658605555628522405324057235472402847585959314774608018954097754737985
      Line 423, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 154975660 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10006 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 154975660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---