KEYMGR_DPE Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.058m	3.123m	37.925ms	25	25	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	0.690s	5.659s	63.087us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	0.880s	5.669s	78.794us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	7.410s	12.420s	728.334us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	3.990s	8.140s	927.774us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.530s	6.666s	32.836us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	0.880s	5.669s	78.794us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.990s	8.140s	927.774us	5	5	100.00
V1		TOTAL				63	63	100.00
V2	intr_test	keymgr_dpe_intr_test	0.590s	5.566s	12.944us	4	4	100.00
V2	alert_test	keymgr_dpe_alert_test	0.580s	3.876s	14.841us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	2.660s	6.658s	123.585us	4	4	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	2.660s	6.658s	123.585us	4	4	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	0.690s	5.659s	63.087us	5	5	100.00
		keymgr_dpe_csr_rw	0.880s	5.669s	78.794us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.990s	8.140s	927.774us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	1.440s	5.648s	150.846us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	0.690s	5.659s	63.087us	5	5	100.00
		keymgr_dpe_csr_rw	0.880s	5.669s	78.794us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.990s	8.140s	927.774us	5	5	100.00
		keymgr_dpe_same_csr_outstanding	1.440s	5.648s	150.846us	20	20	100.00
V2		TOTAL				31	31	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	9.950s	13.196s	6.675ms	6	6	100.00
		keymgr_dpe_tl_intg_err	5.720s	9.497s	234.362us	15	15	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	1.590s	5.605s	475.961us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	1.590s	5.605s	475.961us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	1.590s	5.605s	475.961us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	1.590s	5.605s	475.961us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	2.790s	7.839s	119.295us	3	3	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	9.950s	13.196s	6.675ms	6	6	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	9.950s	13.196s	6.675ms	6	6	100.00
V2S		TOTAL				27	27	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset				0	0	--
V3		TOTAL				0	0	--
		TOTAL				121	121	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.51	97.70	90.39	62.31	75.68	94.61	97.64	17.25

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22