KMAC/MASKED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Max Wall Clock Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 55.590s 59.780s 8.219ms 3 3 100.00
V1 csr_hw_reset kmac_csr_hw_reset 0.850s 4.575s 62.805us 5 5 100.00
V1 csr_rw kmac_csr_rw 0.840s 5.602s 54.409us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 11.900s 15.383s 1.009ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 5.030s 8.759s 143.861us 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 1.940s 6.759s 49.398us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 0.840s 5.602s 54.409us 20 20 100.00
kmac_csr_aliasing 5.030s 8.759s 143.861us 5 5 100.00
V1 mem_walk kmac_mem_walk 0.580s 5.434s 16.813us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.050s 5.374s 63.105us 5 5 100.00
V1 TOTAL 68 68 100.00
V2 long_msg_and_output kmac_long_msg_and_output 20.351m 20.413m 70.187ms 1 1 100.00
V2 burst_write kmac_burst_write 5.019m 5.081m 22.155ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 27.371m 27.428m 69.257ms 5 5 100.00
kmac_test_vectors_sha3_256 28.303m 28.359m 347.786ms 5 5 100.00
kmac_test_vectors_sha3_384 15.798m 15.866m 13.445ms 5 5 100.00
kmac_test_vectors_sha3_512 14.551m 14.611m 31.911ms 5 5 100.00
kmac_test_vectors_shake_128 24.008m 24.064m 86.824ms 5 5 100.00
kmac_test_vectors_shake_256 5.142m 5.196m 57.675ms 5 5 100.00
kmac_test_vectors_kmac 2.250s 6.495s 324.771us 5 5 100.00
kmac_test_vectors_kmac_xof 2.200s 6.414s 378.238us 5 5 100.00
V2 sideload kmac_sideload 3.570m 3.635m 9.384ms 3 3 100.00
V2 app kmac_app 4.110m 4.175m 29.102ms 4 4 100.00
V2 app_with_partial_data kmac_app_with_partial_data 3.706m 3.769m 65.447ms 10 10 100.00
V2 entropy_refresh kmac_entropy_refresh 4.070m 4.122m 37.116ms 5 5 100.00
V2 error kmac_error 5.271m 5.328m 112.925ms 4 4 100.00
V2 key_error kmac_key_error 5.690s 10.321s 6.892ms 3 3 100.00
V2 sideload_invalid kmac_sideload_invalid 5.740s 9.215s 312.764us 5 5 100.00
V2 edn_timeout_error kmac_edn_timeout_error 18.560s 22.151s 4.447ms 3 3 100.00
V2 entropy_mode_error kmac_entropy_mode_error 0.850s 4.160s 129.440us 3 3 100.00
V2 entropy_ready_error kmac_entropy_ready_error 44.930s 48.044s 24.491ms 3 3 100.00
V2 lc_escalation kmac_lc_escalation 17.630s 21.072s 4.068ms 11 11 100.00
V2 stress_all kmac_stress_all 10.860m 10.918m 37.676ms 4 4 100.00
V2 intr_test kmac_intr_test 0.600s 4.565s 52.664us 4 4 100.00
V2 alert_test kmac_alert_test 0.600s 4.079s 22.501us 3 3 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 2.820s 7.212s 351.296us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 2.820s 7.212s 351.296us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 0.850s 4.575s 62.805us 5 5 100.00
kmac_csr_rw 0.840s 5.602s 54.409us 20 20 100.00
kmac_csr_aliasing 5.030s 8.759s 143.861us 5 5 100.00
kmac_same_csr_outstanding 1.860s 6.947s 637.153us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 0.850s 4.575s 62.805us 5 5 100.00
kmac_csr_rw 0.840s 5.602s 54.409us 20 20 100.00
kmac_csr_aliasing 5.030s 8.759s 143.861us 5 5 100.00
kmac_same_csr_outstanding 1.860s 6.947s 637.153us 20 20 100.00
V2 TOTAL 147 147 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 1.520s 5.294s 276.069us 3 3 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 1.520s 5.294s 276.069us 3 3 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 1.520s 5.294s 276.069us 3 3 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 1.520s 5.294s 276.069us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 3.360s 7.701s 862.037us 5 5 100.00
V2S tl_intg_err kmac_sec_cm 57.920s 1.030m 6.727ms 5 5 100.00
kmac_tl_intg_err 3.350s 6.945s 903.253us 5 5 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 3.350s 6.945s 903.253us 5 5 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 17.630s 21.072s 4.068ms 11 11 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 55.590s 59.780s 8.219ms 3 3 100.00
V2S sec_cm_key_sideload kmac_sideload 3.570m 3.635m 9.384ms 3 3 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 1.520s 5.294s 276.069us 3 3 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 57.920s 1.030m 6.727ms 5 5 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 57.920s 1.030m 6.727ms 5 5 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 57.920s 1.030m 6.727ms 5 5 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 55.590s 59.780s 8.219ms 3 3 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 17.630s 21.072s 4.068ms 11 11 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 57.920s 1.030m 6.727ms 5 5 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 4.663m 4.732m 77.253ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 55.590s 59.780s 8.219ms 3 3 100.00
V2S TOTAL 28 28 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 3.950m 4.010m 5.208ms 4 4 100.00
V3 TOTAL 4 4 100.00
TOTAL 247 247 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 26 26 26 100.00
V2S 5 5 5 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.46 98.96 94.12 95.53 74.21 96.15 97.74 97.52

Simulation Wall Clock Time

Target Elapsed
build 00:06:40
run 14:15:03
cov_merge 14:15:15
cov_report 14:15:22
Total 14:15:22