KMAC/UNMASKED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	37.540s	41.462s	7.918ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.780s	5.466s	36.871us	5	5	100.00
V1	csr_rw	kmac_csr_rw	0.780s	5.456s	56.612us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.170s	15.919s	1.192ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	5.030s	9.710s	273.330us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.730s	5.624s	362.991us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.780s	5.456s	56.612us	20	20	100.00
		kmac_csr_aliasing	5.030s	9.710s	273.330us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.580s	5.551s	21.073us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.030s	5.505s	40.280us	5	5	100.00
V1		TOTAL				66	66	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.234m	11.293m	39.781ms	1	1	100.00
V2	burst_write	kmac_burst_write	56.240s	1.002m	5.832ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.307m	17.359m	20.650ms	5	5	100.00
		kmac_test_vectors_sha3_256	24.716m	24.774m	362.500ms	5	5	100.00
		kmac_test_vectors_sha3_384	16.034m	16.102m	45.779ms	5	5	100.00
		kmac_test_vectors_sha3_512	12.132m	12.191m	242.238ms	5	5	100.00
		kmac_test_vectors_shake_128	29.146m	29.214m	221.907ms	5	5	100.00
		kmac_test_vectors_shake_256	24.833m	24.888m	364.729ms	3	3	100.00
		kmac_test_vectors_kmac	1.450s	6.051s	75.841us	5	5	100.00
		kmac_test_vectors_kmac_xof	1.890s	6.041s	224.205us	5	5	100.00
V2	sideload	kmac_sideload	36.780s	40.537s	742.790us	1	1	100.00
V2	app	kmac_app	2.520m	2.572m	13.221ms	4	4	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.825m	2.891m	27.610ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.912m	2.976m	16.322ms	4	4	100.00
V2	error	kmac_error	3.922m	3.986m	88.287ms	5	5	100.00
V2	key_error	kmac_key_error	4.930s	8.266s	4.347ms	3	3	100.00
V2	sideload_invalid	kmac_sideload_invalid	50.050s	54.082s	10.057ms	3	4	75.00
V2	edn_timeout_error	kmac_edn_timeout_error	28.870s	32.109s	1.723ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.750s	31.465s	8.555ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	37.180s	41.782s	27.604ms	3	3	100.00
V2	lc_escalation	kmac_lc_escalation	13.940s	17.279s	3.408ms	10	10	100.00
V2	stress_all	kmac_stress_all	13.442m	13.508m	86.981ms	5	5	100.00
V2	intr_test	kmac_intr_test	0.570s	5.470s	26.143us	4	4	100.00
V2	alert_test	kmac_alert_test	0.570s	4.169s	55.603us	3	3	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.380s	5.694s	865.792us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.380s	5.694s	865.792us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.780s	5.466s	36.871us	5	5	100.00
		kmac_csr_rw	0.780s	5.456s	56.612us	20	20	100.00
		kmac_csr_aliasing	5.030s	9.710s	273.330us	5	5	100.00
		kmac_same_csr_outstanding	1.780s	5.623s	206.021us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.780s	5.466s	36.871us	5	5	100.00
		kmac_csr_rw	0.780s	5.456s	56.612us	20	20	100.00
		kmac_csr_aliasing	5.030s	9.710s	273.330us	5	5	100.00
		kmac_same_csr_outstanding	1.780s	5.623s	206.021us	20	20	100.00
V2		TOTAL				175	176	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.420s	5.669s	84.911us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.420s	5.669s	84.911us	3	3	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.420s	5.669s	84.911us	3	3	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.420s	5.669s	84.911us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.260s	7.841s	245.165us	4	4	100.00
V2S	tl_intg_err	kmac_sec_cm	48.810s	52.025s	6.534ms	3	3	100.00
		kmac_tl_intg_err	3.300s	7.660s	1.840ms	7	7	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.300s	7.660s	1.840ms	7	7	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	13.940s	17.279s	3.408ms	10	10	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	37.540s	41.462s	7.918ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	36.780s	40.537s	742.790us	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.420s	5.669s	84.911us	3	3	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	48.810s	52.025s	6.534ms	3	3	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	48.810s	52.025s	6.534ms	3	3	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	48.810s	52.025s	6.534ms	3	3	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	37.540s	41.462s	7.918ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	13.940s	17.279s	3.408ms	10	10	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	48.810s	52.025s	6.534ms	3	3	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.108m	3.183m	42.871ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	37.540s	41.462s	7.918ms	1	1	100.00
V2S		TOTAL				27	27	100.00
V3	throughput	kmac_throughput				0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.255m	1.309m	4.591ms	2	3	66.67
V3		TOTAL				2	3	66.67
		TOTAL				270	272	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	26	26	25	96.15
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.64	97.28	94.06	99.78	68.84	94.84	97.56	96.11

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 2.kmac_stress_all_with_rand_reset.38875187454339590296935989163513950068379476485233079444566557952978773723787
      Line 336, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12804274896 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 12804274896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:

  • Test kmac_sideload_invalid has 1 failures.

    • 3.kmac_sideload_invalid.2169612835678151219342200995471238806246590527503558656649554001713001175805
      Line 82, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/kmac_unmasked-sim-vcs/3.kmac_sideload_invalid/latest/run.log

        UVM_FATAL @ 10056817775 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0x8db04000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
        UVM_INFO @ 10056817775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---