LC_CTRL/DMI_VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday August 30 2026 03:04:43 UTC

GitHub Revision: 2aab100d17

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Max Wall Clock	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	2.150s	6.164s	478.662us	3	3	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.790s	4.696s	20.637us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	0.760s	4.818s	61.678us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.840s	5.964s	95.601us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.120s	4.807s	33.777us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.320s	4.844s	106.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	0.760s	4.818s	61.678us	20	20	100.00
		lc_ctrl_csr_aliasing	1.120s	4.807s	33.777us	5	5	100.00
V1		TOTAL				58	58	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	5.560s	10.402s	89.332us	1	1	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	11.420s	15.315s	1.424ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.720s	5.735s	34.527us	6	6	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	1.540s	6.054s	152.077us	1	1	100.00
V2	lc_state_failure	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
V2	lc_errors	lc_ctrl_errors	6.160s	11.098s	3.190ms	3	3	100.00
V2	security_escalation	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_prog_failure	1.540s	6.054s	152.077us	1	1	100.00
		lc_ctrl_errors	6.160s	11.098s	3.190ms	3	3	100.00
		lc_ctrl_security_escalation	7.630s	12.640s	2.258ms	5	5	100.00
		lc_ctrl_jtag_state_failure	32.720s	36.107s	3.760ms	3	3	100.00
		lc_ctrl_jtag_prog_failure	8.340s	12.012s	1.609ms	20	20	100.00
		lc_ctrl_jtag_errors	53.550s	56.996s	13.874ms	3	3	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.720s	14.355s	1.420ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	26.340s	30.884s	2.554ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	8.340s	12.012s	1.609ms	20	20	100.00
		lc_ctrl_jtag_errors	53.550s	56.996s	13.874ms	3	3	100.00
		lc_ctrl_jtag_access	8.230s	13.062s	5.424ms	3	3	100.00
		lc_ctrl_jtag_regwen_during_op	25.100s	28.684s	2.808ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.350s	5.962s	296.535us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.400s	5.485s	124.544us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	26.900s	30.024s	26.634ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.400s	13.750s	714.103us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	0.710s	4.663s	64.420us	3	3	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	1.680s	5.550s	712.104us	3	3	100.00
		lc_ctrl_jtag_alert_test	1.470s	4.847s	151.504us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	13.780s	17.535s	2.060ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	0.710s	4.343s	22.081us	3	3	100.00
V2	stress_all	lc_ctrl_stress_all	2.208m	2.265m	7.017ms	7	7	100.00
V2	alert_test	lc_ctrl_alert_test	0.840s	5.435s	23.234us	3	3	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	2.420s	5.855s	623.699us	3	3	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	2.420s	5.855s	623.699us	3	3	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.790s	4.696s	20.637us	5	5	100.00
		lc_ctrl_csr_rw	0.760s	4.818s	61.678us	20	20	100.00
		lc_ctrl_csr_aliasing	1.120s	4.807s	33.777us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.400s	4.835s	56.124us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.790s	4.696s	20.637us	5	5	100.00
		lc_ctrl_csr_rw	0.760s	4.818s	61.678us	20	20	100.00
		lc_ctrl_csr_aliasing	1.120s	4.807s	33.777us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.400s	4.835s	56.124us	20	20	100.00
V2		TOTAL				210	210	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
		lc_ctrl_tl_intg_err	2.410s	6.041s	121.993us	17	17	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.410s	6.041s	121.993us	17	17	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	11.420s	15.315s	1.424ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	10.060s	13.836s	719.811us	3	3	100.00
		lc_ctrl_sec_cm	6.770s	10.968s	874.914us	3	3	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	7.630s	12.640s	2.258ms	5	5	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	5.560s	10.402s	89.332us	1	1	100.00
		lc_ctrl_jtag_state_post_trans	26.340s	30.884s	2.554ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	7.020s	11.105s	322.967us	4	4	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	7.020s	11.105s	322.967us	4	4	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	5.680s	8.848s	1.173ms	1	1	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	6.610s	11.102s	354.663us	3	3	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	6.610s	11.102s	354.663us	3	3	100.00
V2S		TOTAL				28	28	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	57.900s	1.019m	4.806ms	5	7	71.43
V3		TOTAL				5	7	71.43
		TOTAL				301	303	99.34

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.92	97.90	82.54	90.03	97.62	96.99	96.13	96.22

Simulation Wall Clock Time

Target	Elapsed
build	00:06:40
run	14:15:03
cov_merge	14:15:15
cov_report	14:15:22
Total	14:15:22

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.55299323392947560203791168261027016467836299500845939144462011575933337896922
      Line 153, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 437048423 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 437048423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.lc_ctrl_stress_all_with_rand_reset.13628448194812377340075963338899992255507822172613107647972613278223440251309
      Line 18447, in log /nfshome/luism/claude-dv-home/pavona/pavona-work/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5067426332 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5067426332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---